Alibaba open sources four RISC-V cores: XuanTie E902, E906, C906 and C910

Alibaba open source RISC-V cores

Alibaba introduces a range of RISC-V processors in the last few years with the Xuantie family ranging from the E902 micro-controller class core to the C910 core for servers in data centers. This also includes the XuanTie C906 core found in the Allwinner D1 single-core RISC-V processor. While RISC-V is an open standard and there’s a fair share of open-source RISC-V cores available, many commercial RISC-V cores are closed source, but Zhang Jianfeng, President of Alibaba Cloud Intelligence speaking at the 2021 Apsara Conference, announced that T-Head had open-sourced four RISC-V-based Xuantie series processor cores, namely Xuantie E902, E906, C906, and C910, as well as related software and tools. Those are not empty words as we can find the RTL for the four cores released on T-Head Semiconductor’s Github account with the first commits having taken place yesterday. Each repository contains the code and instructions to get started, all under […]

Alibaba T-head RVB-ICE dual-core RISC-V SBC supports Android 10, Debian 11

Alibaba T-Head RISC-V SBC with GPU

The very first RISC-V single board computer with a 3D GPU reveals itself with “Alibaba T-head RVB-ICE” SBC available for pre-order for $399 together with a 7-inch display. The board is based on Alibaba T-Head “ICE” dual-core XuanTie C910 RISC-V processor with a Vivante GC8000UL GPU, and follows the announcement of Android 10 being ported to a RISC-V board earlier this year. Besides the dual-core RISC-V processor clocked at 1.2 GHz, the board is equipped with 4GB LPDDR4, 16GB eMMC flash, and offers Gigabit Ethernet, WiFi and Bluetooth connectivity, as well as a 48-pin GPIO header. But it lacks HDMI output, relying on an LCD interface instead, as well as full-size (Type-A) USB ports with only one micro USB 3.0 OTG port, and a USB-C port for serial console. Alibaba RVB-ICE specifications: SoC – Alibaba T-Head ICE with dual-core XuanTie C910 RISC-V processor @ 1.2 GHz, Vivante GC8000UL GPU, NPU […]

Android 10 ported to RISC-V board powered by Alibaba T-Head XuanTie C910 Processor

Android 10 RISC-V

RISC-V has made a lot of progress in just a few years, but for anything requiring 3D graphics acceleration, it’s not quite there yet. and we only expect RISC-V SoC with Imagination Technologies GPU to come out later this year on hardware such as BeagleV SBC. An OS that will definitely require 3D graphics acceleration is Android, and work has already started since T-Head, a business entity of Alibaba Group specializing in semiconductor chips, has already ported Android 10 (AOSP) on RISC-V architecture with support for graphics and the touchscreen display. The demo above runs on ICE EVB powered by a XuanTie C910 based high-performance SoC board developed by T-Head. Specifically, the ICE SoC integrates two XuanTie C910 cores (RV64) @ 1.2 GHz, one other XuanTie C910V core @ 1.2 GHz with vector extensions, a single-core 3D GPU core [Update: it’s a Vivante GC8000UL GPU], DDR4 memory support, a GMAC […]

XuanTie C906 based Allwinner RISC-V processor to power $12+ Linux SBC’s

Allwinner XuanTie C906 RISC-V Processor

Alibaba unveiled Xuantie-910 RISC-V core (aka XT910) in 2019 for powerful SoC with up to 16 cores, but an update in 2020 revealed the company planned to have a complete RISC-V core family for a wide range of application from low-power microcontrollers to server SoCs. At the time, I just assumed the company planned to keep their cores to themselves, but time proved me wrong as T-Head, the Alibaba subsidiary in charge of developing RISC-V cores, started to cooperate with Allwinner to develop open-source processors, which should lead to low-cost Linux capable RISC-V SBC very soon according to a tweet from Sipeed. Good News: We get first chip which based on XuanTie C906 (RV64GCV), it have abundant interface (HDMI/RGB/DVP/MIPI/GMAC/…), and will be able to run Debian system.Last and most important, the basic dev board price is start at 12.5$ (1% of HiFive Unleashed)。 — Sipeed (@SipeedIO) November 6, 2020 […]

More Details about Alibaba XT910 64-bit RISC-V Core

Xuantie XT902, XT9xx, XT910

Alibaba unveiled XuanTie 910 16-core RISC-V Processor last year with few details except it targetted high-performance 5G, AI, and autonomous driving applications. The company has now provided more details about Alibaba XuanTie 910 (aka XT910) processor during the virtual Hot Chips 2020 conference, and he notably compared the RV64GCV core found in the processor to Arm Cortex-A73 core. Alibaba XT910 main features and specifications: CPU – Up to 16x 64-bit RISC-V (RV64GCV) cores with RISC-V Vector extension and custom Turbo extension in four clusters of four cores; 12-stage out of order; Coremark: 7.1 per MHz Cache – 32KB or 64KB I/D cache per core, up to 8MB L2 cache per cluster FP16-FP64 floating-point unit Vector Computing Unit (aka Vector Engine) for AI acceleration Memory Management – Sv39 MMU + 8/16 PMP Interrupt Controller – Clint + PLIC Process – Final: 12nm FinFET; engineering samples: TSMC 28nm HPC Alibaba RISC-V Turbo […]

Alibaba Unveils XuanTie 910 16-core RISC-V Processor

When Pingtou Ge (Brother Pingtou) Semiconductor Co. was founded by Alibaba in September 2018, the vision was to create groundbreaking chips for production. The company had once been Zhongtianwei, a chip company, which was acquired by Alibaba in April 2018 along with team Aha. On July 25, 2019, it was announced that Brother Pingtou had released the XuanTie 910 (Black Iron 910) 16-Core RISC-V Processor. The company has reported that the processor will be integrated into high-performance end to end 5G chips, AI, and autonomous driving applications. There are conflicting reports that the processor is also known as T-Head, although its name means Black Iron. There has been no firm release date or price as of yet. Open-source technologies are being adopted on a regular basis in China, and the XuanTie 910 is being offered to developers with encouragement to use Berkeley-based open-source ISA with very few intellectual property restrictions. […]