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April 13, 2026 by Jean-Luc Aufranc (CNXSoft) - 6 Comments

Linux 7.0 Release – Main changes, Arm, RISC-V, and MIPS architectures

Linus Torvalds has just released Linux 7.0 on LKML: The last week of the release continued the same “lots of small fixes” trend, but it all really does seem pretty benign, so I’ve tagged the final 7.0 and pushed it out. I suspect it’s a lot of AI tool use that will keep finding corner cases for us for a while, so this may be the “new normal” at least for a while. Only time will tell. Anyway, this last week was a little bit of everything: networking (core and drivers), arch fixes, tooling and selftests, and various random fixes all over the place. Let’s keep testing, and obviously tomorrow the merge window for 7.1 opens. I already have four dozen pull requests pending – thank you to all the early people. Linus This follows the Linux 6.19 release about two months ago, which brought us PCIe link encryption and […]

March 25, 2026March 28, 2026 by Jean-Luc Aufranc (CNXSoft) - 6 Comments

Alibaba XuanTie C950 – A powerful, RVA23-compliant 64-bit RISC-V core for Edge AI computing

Xuantie C950 high performance 64-bit RISC-V CPU

Alibaba has introduced the XuanTie C950 high-performance, 64-bit multi-core CPU IP with an out-of-order superscalar microarchitecture, RVA23 profile compliant, and support for “all optional extensions” such as Vector Crypto, Zacas, and Zama16. The company also says the XuanTie C950 supports the proprietary XuanTie AME (Attached Matrix Extension) ISA and supports integration with the company’s XuanTie TPE (Tensor Processing Engine) IP. The new 64-bit RISC-V core will be found in SoCs with up to eight cores per cluster, targeting high-performance applications, such as cloud computing, edge computing, and AI computing. XuanTie C950 specifications: Architecture – RVA23 Profile Up to 8x cores clocked at 3.2 GHz; 22+/GHz Specint2006 base, or a score of around 70 at 3.2 GHz Pipeline – Superscalar out-of-order microarchitecture with 8-wide decode Floating Point – RISC-V F/D Extension Vector – RISC-V Vector Extension v1.0 with Vector Crypto support Matrix – XuanTie TPE coprocessor integration (AME v0.5) Hypervisor – […]

February 9, 2026 by Jean-Luc Aufranc (CNXSoft) - 2 Comments

Linux 6.19 Release – Main changes, Arm, RISC-V, and MIPS architectures

Linus Torvalds has just released Linux 6.19 on the Linux Kernel Mailing List (LKML): No big surprises anywhere last week, so 6.19 is out as expected – just as the US prepares to come to a complete standstill later today watching the latest batch of televised commercials. The betting man would expect them all to be AI-generated, but maybe some enterprising company decides to buck the trend? Doubtful, but there’s always a slight chance. But for anybody outside the US, maybe taking the newest kernel out for a spin instead is an option? I have more than three dozen pull requests for when the merge window opens tomorrow – thank you to all the early maintainers. And as people have mostly figured out, I’m getting to the point where I’m being confused by large numbers (almost running out of fingers and toes again), so the next kernel is going to […]

July 28, 2025 by Jean-Luc Aufranc (CNXSoft) - 5 Comments

Linux 6.16 Release – Main changes, Arm, RISC-V, and MIPS architectures

Linus Torvalds has just announced the release of Linux 6.16 on LKML: It’s Sunday afternoon, and the release cycle has come to an end. Last week was nice and calm, and there were no big show-stopper surprises to keep us from the regular schedule, so I’ve tagged and pushed out 6.16 as planned. It’s worth noting that the upcoming merge window for 6.17 is going to be slightly chaotic for me: I have multiple family events this August (a wedding and a big birthday), and with said family being spread not only across the US, but in Finland too, I’m spending about half the month traveling. That means that I will try very hard to get most of the merge window done the first week before my travels start, and I already ended upgiving a heads-up on that to the people who tend to send me the most pull requests. […]

August 28, 2023August 28, 2023 by Jean-Luc Aufranc (CNXSoft) - 1 Comment

Linux 6.5 release – Notable changes, Arm, RISC-V and MIPS architectures

Linus Torvalds has just announced the release of Linux 6.5 on the Linux Kernel Mailing List (LKML): So nothing particularly odd or scary happened this last week, so there is no excuse to delay the 6.5 release. I still have this nagging feeling that a lot of people are on vacation and that things have been quiet partly due to that. But this release has been going smoothly, so that’s probably just me being paranoid. The biggest patches this last week were literally just to our selftests. The shortlog below is obviously not the 6.5 release log, it’s purely just the last week since rc7. Anyway, this obviously means that the merge window for 6.6 starts tomorrow. I already have ~20 pull requests pending and ready to go, but before we start the next merge frenzy, please give this final release one last round of testing, ok? Linus The earlier […]

December 14, 2022 by Jean-Luc Aufranc (CNXSoft) - 18 Comments

Sipeed LM4A – T-Head TH1520 RISC-V module to power Raspberry Pi 4 competitor and cluster board

Sipeed LM4A is a quad-core RISC-V system-on-module based on the T-Head TH1520 SoC found in the ROMA laptop and destinated to be found in a Raspberry Pi SBC competitor as well as a cluster board. The LM4A, which stands for Lichee Module 4 Model A, comes with 4GB to 16GB RAM, and up to 64GB flash, and connects to the carrier board through a 260-pin SO-DIMM connector. The TH1520 is one of the rare RISC-V SoCs with a 3D GPU, and the SBC based on LM4A has been shown to outperform the Raspberry Pi 4 in benchmarks as we’ll see below. Sipeed LM4A specifications: SoC – Alibaba T-Head TH1520 quad-core RISC-V Xuantie C910 (RV64GCV) processor @ 2.5 GHz, Xuantie C906 audio DSP @ 800 MHz, low power Xuantie E902 core, 50 GFLOPS Imagination 3D GPU, and 4 TOPS NPU System Memory – 4GB, 8GB, or 16GB RAM Storage – Optional […]

November 4, 2022November 4, 2022 by Jean-Luc Aufranc (CNXSoft) - 2 Comments

T-Head XuanTie C908 RISC-V core targets AIoT applications

We’ve seen two announcements of high-end RISC-V cores this week with the SiFive P670 and Andes AX65 processors each with a 4-way out-of-order pipeline, but Alibaba’s T-Head Semiconductor Xuantie C908 is a little different with a dual-issued, 9-stage in-order pipeline and support for the RISC-V Vector extension acceleration targeting mid-range AIoT applications. The C908 64-bit RISC-V core adopts the RV64GCB[V] instruction and complies with the RVA22 profile for better compatibility with Android and other “rich” operating systems. The company says its performance is between the C906 and C910 cores introduced in 2020 and 2019 respectively. XuanTie C908 highlights: RV32GCB[V] 32-bit and RV64GCB[V] 64-bit RISC-V architectures with Bit manipulation and (optional) Vector operations extensions Support for RV32 COMPAT mode which allows for 64-bit RISC-V CPUs to run 32-bit binary code, and was merged into Linux 5.19. XuanTie extensions, including Instruction, Memory Attributes Extension (XMAE). RVA22 profile compatibility Cluster of 1 to […]

May 2, 2022October 24, 2022 by Jean-Luc Aufranc (CNXSoft) - 17 Comments

Android RISC-V progress update, emulator support, and roadmap to 2023

We’ve first covered Alibaba T-Head work on Android 10 for RISC-V in January 2021, and later that year they started selling the T-Head RVB-ICE dual-core RISC-V board with GPU for software development. The company has now provided an update for Android 12 RISC-V port, instructions to build Android RISC-V to run it in an emulator, as well as a 2022-2023 roadmap. Alibaba T-head is working on hardware platforms, which appears to be similar to T-Head RVB-ICE board, with the following minimal specifications: CPU – At least Dual-core XuanTie C910 (rv64imafdcv) processor GPU – Compatible with OpenGL ES and OpenCL VPU – HW Video/Picture codec Neural Network Accelerator System Memory – 4GB or more DDR Memory Display – MIPI/HDMI Audio – Multi-Channel Audio output & input Camera – ISP with support for multiple MIPI CSI lanes USB interface(s) They built upon the work done on Android 10 to add support for […]