M5Stack ATOM Display Lite adds HDMI output to ESP32 module

ESP32 HDMI output

M5Stack ATOM Display Lite is a kit based on GOWIN Gowin GW1NR-9C FPGA and LT8618SX RGB to HDMI chip designed to add HDMI output up to 720p to the company’s ESP32-based M5Stack ATOM Lite module. The ATOM Lite sees the ATOM Display Lite kit as an SPI display, but the solution outputs the data to an HDMI monitor or TV with up to 1280×720 resolution and can be used for information display, menu board, and more. ATOM Display Lite specifications: Wireless IoT modules – M5Stack ATOM Lite ESP32-PICO-D4 based module with 240MHz dual-core CPU, 520KB SRAM, 4MB flash, Wi-Fi 4 and Bluetooth connectivity FPGA – Gowin GW1NR-9C (PDF datasheet) FPGA with 8,640 LUTs used to simulate SPI TFT-LCD data output, HDMI bridge – Lontium Semi LT8618SX RGB to HDMI chip with 24-bit color depth up to 1280×720 output @ 60 fps (optimized frame rate up to 12 ~ 16FPS) Misc- […]

OSZU3 System-in-Package (SiP) combines AMD Xilinx Zynq UltraScale+ MPSoC with 2GB RAM, PMIC, passive components

OSZU3 system-in-package

Octavo Systems has collaborated with AMD Xilinx for the OSZU3 system-in-package (SiP) that combines Zynq UltraScale+ MPSoC ZU3 with up to 2GB RAM, power management circuitry, and other components into a compact (40×20.5mm) 600-ball BGA package. We’ve already written about other Octavo Systems SiPs in the past with solutions like OSD3358x (TI Sitara AM3358) and OSD32MP15x (STMicro STM32MP1), but the OSZU3 packs a much more powerful and flexible chip with the AMD Xilinx Zynq UltraScale+ MPSoC offering both Cortex-A53 & Cortex-R5F cores, Arm Mali-400 GPU, and FPGA fabric.   Octavo Systems OSZU3 SiP specifications: SoC – AMD Xilinx Zynq UltraScale+ MPSoC ZU3 with CPU – 4x Arm Cortex-A53 up to 1.2GHz, 2x Arm Cortex-R5F up to 500MHz GPU – Arm Mali-400 FPGA 154K System Logic Cells 141K Flip-Flops 71K CLB LUTs 360 DSP Slices 7.6 Mb Block RAM System Memory – 2GB LPDDR4 Storage – 128MB SQPI, and 4K EEPROM (by […]

Silicon Witchery S1 module combines nRF52811 Bluetooth SoC with Lattice iCE40 FPGA

Silicon Witchery S1 module

Sweden-based Silicon Witchery S1 is a tiny module combining Nordic Semi nRF52811 Bluetooth LE SoC with Lattice Semi iCE40 FPGA designed for battery-powered applications leveraging DSP and machine learning (ML) at the edge. The S1 module features just four key components in a tiny 11.5 x 6 mm form factor and targets applications requiring “demanding” algorithms while consuming as little energy as possible. Silicon Witchery S1 module specifications: MCU – Nordic Semi nRF52811 Arm Cortex-M4 MCU @ 64 MHz with Bluetooth 5.2 support including Long Range, Thread support. FPGA – Lattice Semi iCE40 FPGA with 5k LUT and DSP blocks. Storage – 32 Mbit flash storage. Integrated antenna, passives, and crystals. I/Os – 20x castellated holes with 8x FPGA IO include I3C, I2C, SPI, and USB. 2x nRF GPIO pins with ADC and low power wake. SWD pins for debugging Power Supply Lithium battery charging and monitoring. 3x adjustable Vout […]

CLEAR is an open-source FPGA ASIC provided by Efabless’ chipIgnite

CLEAR FPGA board

Open-source SoC designs are available to run on FPGA hardware, but few make it to silicon due to the costs involved. That’s why a couple of years ago the Google SkyWater PDK (process design kit) was released together with an offer to manufacture up to 100 pieces for free to selected designs in collaboration with Efabless. Efabless chipIgnite is an evolution of that offer with $9,750 being enough funds to manufacture 100 QFN or 300 WCSP parts, or alternatively 1,000 parts for $20 each ($20,000). Based on the company’s Caravel template SoC and the openFPGA generator framework, CLEAR open-source FPGA ASIC design is meant to promote and demonstrate the chipIgnite “paid IC creation” solution. You can participate by joining a group buying campaign on GroupGets to get a development board based on CLEAR for $74.99 plus shipping. CLEAR open-source FPGA ASIC features: FPGA – Small 8×8 (64) CLB eFPGA CPU […]

India goes RISC-V with VEGA processors

India VEGA RISC-V processors

One of the main advantages of RISC-V architecture is that it is open, so any organization with the right skills can develop its own cores, and India’s government has taken up this opportunity with the Microprocessor Development Programme (MDP) helping develop VEGA RISC-V cores locally. Thanks to funding by the Ministry of Electronics and Information Technology (MeitY), the Centre for Development of Advanced Computing (C-DAC) managed to design five RISC-V processors ranging from a single-core 32-bit RISC-V microcontroller-class processor to a Linux capable quad-core 64-bit out-of-order processor. Key features of the five VEGA cores developed by the C-DAC: VEGA ET1031 – 32-bit single-core 3-stage in-order RV32IM processor with AHB/AXI4.bus, optional MMU, optional Debug VEGA AS1061 – 64-bit single-core 6-stage in-order RV64IMAFDC processor with 8KB D-cache, 8KB I-cache, FPU, AHB/AXI4 bus VEGA AS1161 – 64-bit single-core 16-stage pipeline out-of-order RV64IMAFDC processor with 32KB D-cache, 32KB I-cache, FPU, AHB/AXI4/ACE bus VEGA AS2161 […]

FOSDEM 2022 schedule with embedded Linux, IoT, automotive… sessions

FOSDEM 2022

While typically taking place in Brussels, Belgium, FOSDEM 2022 will take place online just like FOSDEM 2021 due to COVID-19 restrictions. The good news is that it means anybody can attend it live from anywhere in the world, and makes it more like “FOSDIM”, replacing European with International, in “Free and Open Source Developers’ European Meeting”. FOSDEM 2022 will take place on February 5-6 with 637 speakers, 718 events, and 103 tracks. I’ve made my own little virtual schedule below mostly with sessions from the Embedded, Mobile and Automotive devroom, but also other devrooms including “Computer Aided Modeling and Design”, “FOSS on Mobile Devices”, “Libre-Open VLSI and FPGA”, and others.   Saturday, February 5, 2022 12:30 – 13:00 – Five mysteries in Embedded Linux by Josef Holzmayr Once you start out in embedded Linux, there is a lot to do. Some things are obvious, some less so. First and foremost, […]

Tang Nano 9K FPGA board can emulate PicoRV32 RISC-V soft-core with all peripherals

Tango Nano 9K

Tang Nano 9K FPGA is the third board from Sipeed based on GOWIN FPGA following the original Tang Nano board with 1K LUT and Tang Nano 4K launched last year with GW1NSR-LV4C (aka GW1NSR-4C) FPGA offering 4068 logical units and 64 Mbit PSRAM, plus an Arm Cortex-M3 hard processor. As its name implies, the new board comes with 9K LUTs, as well as 64 Mbit PSRAM, 32 Mbit Flash, a micro SD card, and video I/O (HDMI, RGB LCD connector) that makes it suitable to run Verilog HDL code emulating a PicoRV32 RISC-V soft-core with all peripherals. Tang Nano 9K FPGA board specifications: FPGA – GOWIN LittleBee GW1NR-9/GW1NR-LV9 8,640 logical units (LUTs) 6,480 flip-flop 17,280 bits shadow SRAM (SSRAM) 486 Kbit block SRAM (BSRAM) 64 Mbit PSRAM 608 Kbit user flash 2x PLL Up to 276x user I/O Storage – 32 Mbit SPI flash. MicroSD card socket Display I/F HDMI […]

CaribouLite RPi HAT open-source SDR Raspberry Pi HAT tunes up to 6 GHz (Crowdfunding)

Raspberry Pi HAT SDR 6 GHz

CaribouLite RPi HAT is an open-source dual-channel software-defined radio (SDR) Raspberry Pi HAT – or rather uHAT – that works in the sub-GHz ISM range and optionally the 30 MHz – 6 GHz range for the full version. Developed by Israel-based CaribouLabs, the micro HAT is equipped with a Lattice Semi ICE40LP1K FPGA, a Microchip AT86RF215 RF transceiver, two SMA antenna connectors, a Pmod expansion connector, and designed for any Raspberry Pi board with a 40-pin GPIO header. CaribouLite RPi HAT specifications: FPGA – Lattice Semi ICE40LP with 1.28 kLE RF Chipset – Microchip AT86RF215 Sub-GHz / 2.4GHz transceiver Qorvo’s RFFC5072 integrated Mixer IC (for full version only) Tuning Range CH1 Full version – 30 MHz – 6 GHz ISM version – 2.4 – 2.4835 GHz CH2 – Sub-1GHz Max Sampling Rate – 4 MSPS ADC/DAC Resolution – 13-bit Max RF Bandwidth – 2.5 MHz Transmit Power – up to […]