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Posted on by Jean-Luc Aufranc (CNXSoft) - 3 Comments on Broadcom updates its Wi-Fi 8 access point chips portfolio with BCM4918 APU, BCM6714 and BCM6719 dual-band radios

Broadcom updates its Wi-Fi 8 access point chips portfolio with BCM4918 APU, BCM6714 and BCM6719 dual-band radios

Broadcom Wi-Fi 8 chips BCM4918 BCM6719 BCM6714

Broadcom has just announced the launch of its next-generation chips for Wi-Fi 8 access points at CES 2026 with the BCM4918 Accelerated Processing Unit (APU), and two new dual-band Wi-Fi 8 radios: BCM6714 and BCM6719. The last two build upon the Broadcom BCM6718 WiFi 8 tri-band SoC with different antenna configurations, namely 4×4 2.4GHz and 4×4 5 GHz for the BCM6719, and 3×3 2.4GHz and 4×4 5 GHz for the BCM6714, and integrated 2.4 GHz PAs. The AP4918 builds upon the AP4916, but I was unable to obtain information about the improvements from a company representing Broadcom. Broadcom BCM4918 Wi-Fi 8 APU BCM4918 key features: High-performance Quad-core Armv8 CPU complex for general-purpose software workloads Integrated Broadcom Neural Engine (BNE) for on-device AI/ML inference and acceleration Advanced networking engines to offload both wired and wireless data paths, enabling complete CPU bypass of all networking traffic Integrated cryptographic protocol acceleration end-to-end data […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 9 Comments on Allwinner V861 dual-core 64-bit RISC-V AI Camera SiP features 128MB DDR3L, 4K H.265/H.264 video encoder

Allwinner V861 dual-core 64-bit RISC-V AI Camera SiP features 128MB DDR3L, 4K H.265/H.264 video encoder

Allwinner V861 Block Diagram

Allwinner V861 is a new dual-core 32-bit/64-bit RISC-V C907 system-in-package (SiP) with 128MB on-chip DDR3L and designed for 4K AI camera applications with a 1 TOPS AI NPU. The chip also features a 32-bit RISC-V E907 low-power core, a 4Kp25 H.264/H.265 video encoder, a 1080p60 JPEG video decoder and encoder, MIPI CSI and parallel camera interfaces, audio codec with input and output interfaces, Fast Ethernet, USB 2.0, and a range of digital and analog I/Os. Allwinner V861M3-XXX specifications: CPU Dual-Core RISC-V XuanTie C907 (RV64GCBV/RV32GGCBV) clocked up to 1.4GHz with RVV 1.0 extensions Single-core RISC-V XuanTie E907 (RV32IMAFC) clocked up to 800MHz VPU Video Encoder H.264/H.265 up to  4K @ 25fps (M)JPEG up to 8192×8192 Video Decoder – (M)JPEG up to 1080p60 AI accelerator – 1 TOPS (INT8) NPU dubbed “AI-ISP 2.0” Memory 128MB DDR3/DDR3L (SiP) “SQPI” PSRAM interface Storage QSPI flash eMMC 4.41 SDIO 2.0/3.0 Display – SPI interface Camera […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 1 Comment on VEGA AS2161 “DHRUV64” – A 1GHz dual-core 64-bit RISC-V microprocessor designed in India

VEGA AS2161 “DHRUV64” – A 1GHz dual-core 64-bit RISC-V microprocessor designed in India

VEGA AS2161 block diagram

The Government of India has been investing to spur up its semiconductor design and manufacturing industry at least since 2018/2019 with the SHAKTI and AJIT microprocessors. In 2022, they decided to focus on the RISC-V architecture with the VEGA processor family, starting with the THEJAS32 (VEGA ET1031) and THEJAS64 (VEGA AS1061) microprocessors, and the former was eventually found in the ARIES v3.0 Arduino UNO-inspired development board. Things continue to progress nicely, albeit slowly, and the government has now announced the launch of the DHRUV64 (VEGA AS2161) dual-core 64-bit RISC-V MPU clocked at 1 GHz and supporting Linux, which it describes as “a fully indigenous microprocessor developed by the Centre for Development of Advanced Computing (C-DAC) under the Microprocessor Development Programme (MDP)”. VEGA AS2161 (DHRUV64) specifications highlights: Architecture – RISC-V 64G (RV64IMAFD) Instruction Set 13-16 stage out-of-order pipeline implementation. Advanced branch predictor – BTB, BHT, RAS. Harvard architecture, separate Instruction and […]

Posted on by Debashis Das - 7 Comments on Up to 16-core AMD EPYC Embedded 2005 Series Zen 5 processors support up 28 PCIe Gen5 lanes, offer 10-year availability

Up to 16-core AMD EPYC Embedded 2005 Series Zen 5 processors support up 28 PCIe Gen5 lanes, offer 10-year availability

AMD EPYC Embedded 2005 Series Processors

After the release of the high-performance EPYC Embedded 9005, AMD has now introduced the EPYC Embedded 2005 Series, a mid-range processor family also based on the “Zen 5” architecture and designed for space-constrained networking, storage, and industrial edge applications. The new SoCs feature up to 16 cores (32 threads) with 64 MB L3 cache, support dual-channel DDR5-5600 memory with ECC, and offer 28 lanes of PCIe Gen5 connectivity. It also supports advanced RAS capabilities, BMC, PCIe Hot Plug, multi-SPI ROM, and AMD Infinity Guard security. The processors come in a compact 40 x 40mm BGA package, which, according to AMD, is up to 2.4x smaller than competing enterprise solutions (Intel Xeon 6500P-B). Yet, they are designed for 24/7 operation, with up to 10 years of availability with full open-source software support. These features make it suitable for networking switches/routers, cold storage systems, aerospace, robotics, and other high-reliability embedded infrastructure. EPYC […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 6 Comments on Three high-performance RISC-V processors to watch in H2 2025: UltraRISC UR-DP1000, Zhihe A210, and SpacemIT K3

Three high-performance RISC-V processors to watch in H2 2025: UltraRISC UR-DP1000, Zhihe A210, and SpacemIT K3

UR-DP1000 Block Diagram

Some high-performance RISC-V processors are in the pipeline for the rest of the year 2025, namely UltraRISC UR-DP1000, Zhihe A210, and SpacemIT K3. We currently have limited information about each of those processors, but let’s see what information we can gather from the web, mostly as a result of the recent RISC-V Summit in China. UltraRISC UR-DP1000  – Octa-core 64-bit RISC-V SoC The first SoC is the UR-DP1000 octa-core from UltraRISC (the website loads slowly, and I could not find anything about the UR-DP1000 there). It will be used in Shenzhen Milk-V Technology’s Titan mini-ITX motherboard, and Sipeed also posted the slide above on X. Preliminary UR-RP1000 specifications: CPU 8x 64-bit RISC-V UR-CP100 “RV64GCBHX” cores up to 2.0 GHz Two 4x core cluster design with 4MB L3 cache each, and a total of 16MB cache. SPECCPU2006 single-core INT @ 10.4/GHz; single-core FP @ 12/GHz Fully RVA22 compliant, and “Compliant with […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 65 Comments on Rockchip unveils RK3668 10-core Arm Cortex-A730/Cortex-A530 SoC with 16 TOPS NPU, RK182X LLM/VLM co-processor

Rockchip unveils RK3668 10-core Arm Cortex-A730/Cortex-A530 SoC with 16 TOPS NPU, RK182X LLM/VLM co-processor

Rockchip RK3668

The Rockchip Developer Conference 2025 (RKDC!2025) is now taking place in Fuzhou, China, with some interesting announcements such as the Rockchip RK3668 10-core Arm Cortex-A730/A530 processor with a 16 TOPS NPU and the RK182X RISC-V co-processor with support for up to 7B parameters LLM (large Language Model)or VLM (Vision Language Model). Rochchip RK3668 10-core Armv9 SoC Let’s have a look at the Rockchip RK3668 SoC, which looks quite similar to the RK3688 SoC unveiled last year, but with some differences. Preliminary Rockchip RK3668 specifications: CPU – 4x Cortex-A730 + 6x Cortex-A530 Armv9.3 cores delivering around 200K DMIPS; note: neither core has been announced by Arm yet GPU – Arm Magni GPU delivering up to 1-1.5 TFLOPS of performance AI accelerator – 16 TOPS RKNN-P3 NPU VPU – 8K 60 FPS video decoder ISP – AI-enhanced ISP supporting up to 8K @ 30 FPS Memory – LPDDR5/5x/6 up to 100 GB/s […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 4 Comments on Allwinner H135 RISC-V multimedia SoC is made for projectors and KVM solutions

Allwinner H135 RISC-V multimedia SoC is made for projectors and KVM solutions

Allwinner H135

The Allwinner H135 is a 64-bit RISC-V multimedia SoC officially designed for low-cost projectors. However, support for HDMI Rx and MJPEG 1080p60 video encoding also makes it suitable for entry-level KVM (Keyboard, Video, and Mouse) solutions. The H135 is based on the XuanTie C906 core, supports up to 256MB DDR2/DDR3/DDR3L, integrates a 1080p60 H.265/H.264 video decoder, MIPI DSI, dual-channel LVDS, and RGB888 display interfaces, and plenty of peripherals such as USB, SDIO, UART, SPI, PWM, GPIO, and more. Allwinner H135 specifications: CPU – XuanTie C906 RISC-V CPU with 64 KB I-cache + 64 KB D-cache Display Engine Allwinner Awonder1.1 Lite post processing Keystone correction in online mode and [-360°,360°] rotation in offline mode De-interlace (DI) up to 1920×1080 @ 60fps G2D hardware accelerator with rotate and mixer functions VPU Video decoding – H.265, H.264, H.263, MPEG-1/2/4, and VC-1  up to 1080p60 Image decoding – JPEG up to 1080p60 Video encoding […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 7 Comments on Vortex86EX3 Twin Core x86 processor targets legacy industrial applications running Windows, Linux, DOS, WinCE, QNX…

Vortex86EX3 Twin Core x86 processor targets legacy industrial applications running Windows, Linux, DOS, WinCE, QNX…

Vortex86EX3 x86 industrial SoC

D&MP Vortex86EX3 is a Twin Core x86 SoC for industrial applications with a master CPU and a Slave CPU,  each capable of running an operating system independently, be it Windows 10 IoT, Linux, legacy OS like WinCE or DOS, or an RTOS like QNX. Like its predecessors, such as the DM&P Vortex86EX2 or Vortex86DX3, the Vortex86EX3 – also written Vortex86 EX3 –  supports older PCI and ISA interfaces, as well as more recent interfaces such as PCIe, and the usual serial, CAN Bus, and GPIO found in this type of processor. The Vortex86EX3 is the most powerful x86 SoC from the company so far, with two cores clocked at up to 1.2 GHz to 1.6 GHz. The comparison table below lists the specifications and main features of the Vortex86DX3 (2015), Vortex86EX2 (2019), and the new Vortex86EX3. The Vortex86EX3 is not listed on the Vortex86.com website yet, and instead, I found […]