Posted on - 5 Comments on BOOM Open Source RISC-V Core Runs on Amazon EC2 F1 Instances

BOOM Open Source RISC-V Core Runs on Amazon EC2 F1 Instances

BOOM RISC-V Core Block Diagram

The Berkeley Out-of-Order Machine (BOOM) is an open source RV64G RISC-V core written in the Chisel hardware construction language, and mainly ASIC optimized. However, it is also usable on FPGAs, and developers support the FireSim flow to run BOOM at over 90 MHz on Xilinx Ultrascale+ FPGAs found in Amazon EC2 F1 instances. The BOOM core was created at the University of California, Berkeley in the Berkeley Architecture Research group, in order to create a high performance, synthesizable, and parameterizable core for architecture research. Key features of BOOM core: ISA – RISC-V (RV64G) Synthesizable FPGA support Parameterized Floating Point (IEEE 754-2008) Atomic Memory Op Support Caches & Virtual Memory Boots Linux Privileged Arch v1.11 External Debug BOOM is said to be inspired by the MIPS R10k and the Alpha 21264 out–of–order processors, based on a unified physical register file design (aka as “explicit register renaming”). The source code for the core can be found on Github, and documentation here, which …

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Posted on - 6 Comments on MicroSemi Introduces PolarFire FPGA & RISC-V SoC

MicroSemi Introduces PolarFire FPGA & RISC-V SoC

Polaris FPGA + RISC-V SoC

In the past we’ve covered SoCs comprised of Arm cores and FPGA fabric via Xilinx Zynq-7000 series SoCs and Zynq UltraScale+ series MPSoCs, respectively featuring up to two Arm Cortex A9 cores, and up to four Cortex A53 cores. MicroSemi has now announced an alternative, not based on Arm cores, but instead based on SiFive U54-MC RISC-V cores combined with PolarFire FPGA fabric. PolarFire FPGA RISC-V SoC key features & specifications: FPGA – Microsemi PolarFire FPGA Processor Cores – Up to 4x SiFive U54-MC RISC-V cores clocked at up to 1.5GHz (performance similar to Cortex-A35 cores); 28nm process Deterministic Coherent Multi-core CPU Cluster Deterministic L2 Memory Subsystem System Memory I/F –  Integrated DDR4/LPDDR4 Controller and PHY Storage – Secure Boot, 128K Boot Flash Debug capability Rich I/Os Low Power – Low static power; power optimized transceivers, up to 50% lower power compared to SRAM based FPGAs So we don’t have the full picture just yet, and we’ll have to wait …

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Posted on - 3 Comments on Open Source Hardware SpiderSoM System-on-Module Features Intel MAX 10 FPGA

Open Source Hardware SpiderSoM System-on-Module Features Intel MAX 10 FPGA

aries embedded spidersom

When embedded systems companies offer a system-on-module (SoM) and a baseboard, the later is usually open source hardware with all design files provided so that customers can leverage the work for their own baseboard, but files for the SoM are normally not released to customers. Intel MAX 10 FPGA based Aries SpiderSoM and SpiderBase change that, as the company has decided to release both the module and carrier board KiCAD designs under a CERN OHL v1.2 license. SpiderSoM system-on-module specifications: FPGA – Intel MAX 10 FPGA in F256 package from 10M04DC to 10M50DA System Memory – Optional 128/256/512MB DDR3 DRAM for 10M 16/25/40/50 FPGAs Storage – Optional 4 MB SPI NOR, optional 4 GB eMMC flash 230-pin MxM2 edge connector with 178x FPGA GPIO pins, including 13 LVDS transmitters and 54 receivers Misc – RTC with battery backup,  programmable clock generator and PLL, with optional external reference input Power Supply Programmable high-efficient PMIC, FPGA IO voltages are configurable optional Li-Ion/Li-Pol …

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Posted on - 1 Comment on Embedded Recipes 2018 Videos and Slides Released

Embedded Recipes 2018 Videos and Slides Released

Upstream Multimedia Amlogic-SoC-Embedded Recipes 2018 Videos

Embedded Recipes 2018 happened in Mozilla building in Paris, France on September 24 & 25, where developers talked about “open source solutions in the embedded world: developer, contributor, tools, platforms…” We previously mentioned the event in a post about an open source video decoder driver for Amlogic S905, S905X and S912 processors with BayLibre scheduled to talk about their work there. There’s now released slides and videos for the event for all sessions including: SoC+FPGA support in 2018 by Marek Vasut Shared memory and telemetry by Yves-Marie Morgan Updating an embedded system with swupdate by Charles-Antoine Couret Finding sources of latency in your system by Steven Rostedt Io(M)T Security: A year in review by Rayna Stamboliyska Using yocto to generate container images for yocto by Jérémy Rosen linuxboot by Jean-Marie Verdun and  Trammell Hudson End-to-end software production for embedded by Guy Lunardi WooKey: the USB Battlefront Warrior by Mathieu Renard, Ryad Benadjila EBBR: Standard Boot for Embedded Platforms by Alexander …

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Posted on - 29 Comments on LicheeTang Anlogic EG4S20 FPGA Board Targets RISC-V Development

LicheeTang Anlogic EG4S20 FPGA Board Targets RISC-V Development

LicheeTang

LicheePi has already made some interested little development board in the past with products such as LicheePi Zero, and the recently-announced SD card sized LicheePi Nano board, but their  latest development board may ever be more intriguing. LicheeTang features Anlogic EG4S20 FPGA – unrelated to Amlogic – which run a RISC-V softcore,  and all is packaged in a small small form factor as we’ve come to expect with LicheePi boards. LicheeTang specifications: FPGA – Anlogic EG4S20BG256 with 20K logic unit (LUT4/LUT5 hybrid architecture), about 130KB SRAM, 64MBit SDRAM Storage – 8Mbit flash, micro SD card slot, optional SPI NOR flash Expansion Connectors FPC40P socket for RGB LCD, VGA adapter board, or high speed (12-bit 1MSPS) DAC module FPC24P socket for DVP camera, or high speed ADC module Through holes and castellated holes exposing over 130 I/Os Debugging – FPGA JTAG chip connected over micro USB port Misc – RGB LED Power Supply – 5V via micro USB port; 3-channel DCDC …

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Posted on - 2 Comments on BladeRF 2.0 USB 3.0 Software Defined Radio Launched for $480 and Up

BladeRF 2.0 USB 3.0 Software Defined Radio Launched for $480 and Up

BladeRF 2.0 Micro

Around 5 years ago, several affordable FPGA based open source software defined radio boards launched including HackRF, BladeRF x40 / x115, and  USRP B200. The company behind BladeRF has now launched an update of their boards with Blade RF 2.0 coming in two versions namely bladeRF 2.0 micro xA4 and bladeRF 2.0 micro xA9 supporting the same 47MHz to 6GHz frequency range, and 61.44MHz sampling rate, but the latter comes with a more powerful 301KLE Cyclone V FPGA. BladeRF 2.0 hardware specifications: FPGA Micro xA4 – Intel / Altera Cyclone V FPGA with 49 kLE Micro xA9 – Intel / Altera Cyclone V FPGA with 301 kLE Analog Devices RF Transceiver 47 MHz to 6 GHz frequency range 2×2 MIMO, 61.44 MHz sampling rate 56 MHz filtered bandwidth (IBW) Automatic gain control (AGC) Real- time custom gain control tables controlled via SPI and discrete external input pins Automatic IQ and DC offset correction 128-tap digital FIR filtering USB 3.0 SuperSpeed …

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Posted on - 1 Comment on UltraZed-EV Starter Kit Support Simultaneous 4K Encoding and Decoding with Xilinx Zynq UltraScale+ EV MPSoC

UltraZed-EV Starter Kit Support Simultaneous 4K Encoding and Decoding with Xilinx Zynq UltraScale+ EV MPSoC

UltraZed EV Starter Kit

Xilinx unveiled Zynq UltraScale+ MPSoC‘s combining Arm Cortex A53/R5 cores with FPGA fabric back in 2015. and we started to see development boards and products based on the solution starting in 2017 with offerings such as AXIOM Board, TRENZ TE0808 SoM, or more recently 96Boards compliant Ultra96 development board. All last three boards have one thing in common: they all use an Zynq UltraScale+ GC MPSoC that adds a Mali-400MP2 GPU to CG MPSoC family. But there’s also a third EV family which standards for “Embedded Vision”, and adds support for 4K H.264 / H.265 hardware video codec capable of simultaneous encode and decode. The platform targets multimedia, automotive ADAS, surveillance, and other embedded vision applications. So far, I don’t think I had seen any boards based on Ultrascale+ EV MPSoC, but AVNet  – following up on their UltraZed-EG starter kit – has now launched an UltraZed-EV starter kit powered by UltraScale+ MPSoC XCZU7EV-1FBVB900E. The kit is comprised of a …

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Posted on - 1 Comment on Air-T Artificial Intelligence Radio Transceiver SDR Platform Combines NVIDIA Jetson TX2 and Xilinx Artix-7 FPGA (Crowdfunding)

Air-T Artificial Intelligence Radio Transceiver SDR Platform Combines NVIDIA Jetson TX2 and Xilinx Artix-7 FPGA (Crowdfunding)

If often write about low end and cheaper hardware on this blog, but not in this post. Deepwave Digital Air-T (Artificial Intelligence Radio – Transceiver) is a high-end software defined radio platform with continuous frequency coverage from 300 MHz to 6 GHz. The board combines AD9371 RFIC transceiver providing up to 2 x 2 MIMO of 100 MHz of receiving bandwidth, a Xilinx Artix-7 FPGA, and NVIDIA Jetson TX2 module. Air-T hardware specifications & key features: Software-defined Radio Analog Devices 9371 2×2 MIMO transceiver 2 x RX channels (100 MHz each) 2 x TX channels (100 MHz each) Auxiliary RX channels: Observation & Sniffer. Note: Can use either Observation or Sniffer at one time; utilizes one of the RX channels NVIDIA Jetson TX2 for processing 256 NVIDIA CUDA core GPU 6 CPU cores – 2x NVIDIA Denver2, 4x Arm Cortex-A57 8GB RAM 32GB eMMC flash Xilinx Artix-7 FPGA with75k logic cells External Storage – SATA, SD card slot, or via …

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