Posts Tagged ‘fpga’

LimeSDR Mini is a $135 Open Source Hardware, Full Duplex USB SDR Board (Crowdfunding)

September 18th, 2017 13 comments

LimeSDR open source hardware software defined radio was launched last year with the promise of integration with Ubuntu Snap Store allowing to easily download and install various radio implementations such as LTE, WiFi, Bluetooth, LoRa, etc… It was offered for $200 and up as part of a crowdfunding campaign, but Lime Microsystems is back on CrowdSupply with a cheaper and low end version aptly called LimeSDR Mini.LimeSDR mini specifications:

  • FPGA – Intel Altera Max 10 (10M16SAU169C8G) with 16K Logic gates, 549 KB M9K memory, 2,368 KB user flash memory
  • Storage –  4 MB flash memory for data; 2x128KB EEPROM for RF transceiver MCU firmware and data
  • RF
    • Lime Microsystems LMS7002M RF transceiver
    • Tx & Rx SMA connectors
    • Frequency range – 10 MHz to 3.5 GHz
    • RF bandwidth – 30.72 Mhz
    • Sample Rate – 30.72 MSps with 12-bit sample depth
    • Power Output (CW): up to 10 dBm
  • USB – 1x USB 3.0 port via FTDI FT601 controller chip
  • Expansion – 8-pin FPGA GPIO header
  • Misc – 2x  dual color LEDs, JTAG
  • Power – USB or external power supply
  • Dimensions – 69 mm x 31.4 mm

The company also put together a table to compare LimeSDR to LimeSDR Mini and other product on the markers from the dirty cheap RTL-SDR stick to more expensive and advanced solutions like Ettus B210.

The new LimeSDR Mini board will support the same development tools such as LimeSuite, and Snappy Ubuntu Core apps as its old brother, although I’m not quite sure about the status about the app store, as they did not provide that many details. The board will also be open source hardware, with hardware design files that should be released on MyriadRF’s Github account shortly before or after shipping. The company will also offer some accessories for the board such as an acrylic enclosure, and three SMA antennas optimized for 800-960 MHz, 1710-2170 MHz, and 2400-2700 MHz.

LimeSDR Mini Prototype (no SMA connectors) in Acrylic Case

The goal is to raise at least $100,000 for mass production, and after a few days they’re off to a good start with over $76,000 pledged. All 500 $99 early bird rewards are gone, but you can still pledge $139 for the board with delivery planned for December 31, 2017. Shipping is free to the US, and $10 to the rest of the world.

Embedded Linux Conference & Open Source Summit Europe 2017 Schedule

August 27th, 2017 3 comments

The Embedded Linux Conference & IoT summit 2017 took place in the US earlier this year in February, but there will soon be a similar event with the Embedded Linux Conference *& Open Source Summit Europe 2017 to take up in Europe on October 23 – 25 in Prague, Czech Republic, and the Linux Foundation has just published the schedule. It’s always useful to find out what is being discussed during such events, even if you are not going to attend, so I went through the different sessions, and compose my own virtual schedule with some of the ones I find the most interesting.

Monday, October 23

  • 11:15 – 11:55 – An Introduction to SPI-NOR Subsystem – Vignesh Raghavendra, Texas Instruments India

Modern day embedded systems have dedicated SPI controllers to support NOR flashes. They have many hardware level features to increase the ease and efficiency of accessing SPI NOR flashes and also support different SPI bus widths and speeds.

In order to support such advanced SPI NOR controllers, SPI-NOR framework was introduced under Memory Technology Devices (MTD). This presentation aims at providing an overview of SPI-NOR framework, different types of NOR flashes supported (like SPI/QSPI/OSPI) and interaction with SPI framework. It also provides an overview of how to write a new controller driver or add support for a new flash device.

The presentation then covers generic improvements done and proposed while working on improving QSPI performance on a TI SoC, challenges associated when using DMA with these controllers and other limitations of the framework.

  • 12:05 – 12:45 – Free and Open Source Software Tools for Making Open Source Hardware – Leon Anavi, Konsulko Group

The open source hardware movement is becoming more and more popular. But is it worth making open source hardware if it has been designed with expensive proprietary software? In this presentation, Leon Anavi will share his experience how to use free and open source software for making high-quality entirely open source devices: from the designing the PCB with KiCAD through making a case with OpenSCAD or FreeCAD to slicing with Cura and 3D printing. The talk will also provide information about open source hardware licenses, getting started guidelines, tips for avoiding common pitfalls and mistakes. The challenges of prototyping and low-volume manufacturing with both SMT and THT will be also discussed.

  • 14:20 – 15:00 – Introduction to SoC+FPGA – Marek Vašut, DENX Software Engineering GmbH

In this talk, Marek introduces the increasingly popular single-chip SoC+FPGA solutions. At the beginning, the diverse chip offerings from multiple vendors are introduced, ranging from the smallest IoT-grade solutions all the way to large industrial-level chips with focus on their software support. Mainline U-Boot and Linux support for such chips is quite complete, and already deployed in production. Marek demonstrates how to load and operate the FPGA part in both U-Boot and Linux, which recently gained FPGA manager support. Yet to fully leverage the potential of the FPGA manager in combination with Device Tree (DT) Overlays, patches are still needed. Marek explains how the FPGA manager and the DT Overlays work, how they fit together and how to use them to obtain a great experience on SoC+FPGA, while pointing out various pitfalls.

  • 15:10 – 15:50 – Cheap Complex Cameras – Pavel Machek, DENX Software Engineering GmbH

Cameras in phones are different from webcams: their main purpose is to take high-resolution still pictures. Running preview in high resolution is not feasible, so resolution switch is needed just before taking final picture. There are currently no applications for still photography that work with mainline kernel. (Pavel is working on… two, but both have some limitations). libv4l2 is doing internal processing in 8-bit, which is not enough for digital photography. Cell phones have 10 to 12-bit sensors, some DSLRs do 14-bit depth.

Differences do not end here. Cell phone camera can produce reasonable picture, but it needs complex software support. Auto-exposure / auto-gain is a must for producing anything but completely black or completely white frames. Users expect auto-focus, and it is necessary for reasonable pictures in macro range, requiring real-time processing.

  • 16:20 – 17:00 – Bluetooth Mesh with Zephyr OS and Linux – Johan Hedberg, Open Source Technology Center, Intel

Bluetooth Mesh is a new standard that opens a whole new wave of low-power wireless use cases. It extends the range of communication from a single peer-to-peer connection to a true mesh topology covering large areas, such as an entire building. This paves the way for both home and industrial automation applications. Typical home scenarios include things like controlling the lights in your apartment or adjusting the thermostat. Although Bluetooth 5 was released end of last year, Bluetooth Mesh can be implemented on any device supporting Bluetooth 4.0 or later. This means that we’ll likely see very rapid market adoption of the feature.

The presentation will give an introduction to Bluetooth Mesh, covering how it works and what kind of features it provides. The talk will also give an overview of Bluetooth Mesh support in Zephyr OS and Linux and how to create wireless solutions with them.

  • 17:10 – 17:50 – printk() – The Most Useful Tool is Now Showing its Age – Steven Rostedt, VMware

printk() has been the tool for debugging the Linux kernel and for being the display mechanism for Linux as long as Linux has been around. It’s the first thing one sees as the life of the kernel begins, from the kernel banner and the last message at shutdown. It’s critical as people take pictures of a kernel oops to send to the kernel developers to fix a bug, or to display on social media when that oops happens on the monitor on the back of an airplane seat in front of you.

But printk() is not a trivial utility. It serves many functionalities and some of them can be conflicting. Today with Linux running on machines with hundreds of CPUs, printk() can actually be the cause of live locks. This talk will discuss all the issues that printk() has today, and some of the possible solutions that may be discussed at Kernel Summit.

  • 18:00 – 18:45 – BoF: Embedded Linux Size – Michael Opdenacker, Free Electrons

This “Birds of a Feather” session will start by a quick update on available resources and recent efforts to reduce the size of the Linux kernel and the filesystem it uses.

An ARM based system running the mainline kernel with about 3 MB of RAM will also be demonstrated. If you are interested in the size topic, please join this BoF and share your experience, the resources you have found and your ideas for further size reduction techniques!

Tuesday, October 24

  • 10:55 – 11:35 – Introducing the “Lab in a Box” Concept – Patrick Titiano & Kevin Hilman, BayLibre

Continuous Integration (CI) has been a hot topic for long time. With the growing number of architectures and boards, it becomes impossible for maintainers to validate a patch on all configurations, making it harder and harder to keep the same quality level without leveraging CI and test automation. Recent initiatives like LAVA,, Fuego, (…) started providing a first answer, however the learning curve remains high, and the HW setup part is not covered.

Baylibre, already involved in, decided, as part of the AGL project, to go one step further in CI automation and has developed a turnkey solution for developers and companies willing to instantiate a LAVA lab; called “Lab in a Box”, it aims at simplifying the configuration of a board farm (HW, SW).

Motivations, challenges, benefits and results will be discussed, with a demo of a first “Lab in a Box” instantiation.

  • 11:45 – 12:25 – Protecting Your System from the Scum of the Universe – Gilad Ben-Yossef, Arm Holdings

Linux based systems have a plethora of security related mechanisms: DM-Crypt, DM-Verity, Secure Boot, the new TEE sub-system, FScrypt and IMA are just a few examples. This talk will describe these the various systems and provide a practical walk through of how to mix and match these mechanisms and design them into a Linux based embedded system in order to strengthen the system resilience to various nefarious attacks, whether the system discussed is a mobile phone, a tablet, a network attached DVR, a router, or an IOT hub in a way that makes maximum use of the sometime limited hardware resources of such systems.

  • 14:05 – 14:45 – Open Source Neuroimaging: Developing a State-of-the-Art Brain Scanner with Linux and FPGAs – Danny Abukalam, Codethink

Neuroimaging is an established medical field which is helping us to learn more about how the human brain works, the most complex human organ. This talk aims to cover neuroimaging systems, from hobbyist to professional, and how open source has been used to build state-of-the-art systems. We’ll have a look the general problem area, why open source was a good fit, and some examples of solutions including a commercial effort that we have been involved in bringing to market. Typically these solutions consist of specialist hardware, a bespoke software solutions stack, and a suite to manage and process the vast amounts of data generated during the scan. Other points of interest include how we approached building a maintainable and upgradeable system from the outset. We’ll also talk about future plans for neuroimaging, future ideas for hardware & discuss areas lacking good open source solutions.

  • 14:55 – 15:35 – More Robust I2C Designs with a New Fault-Injection Driver – Wolfram Sang, Renesas

It has its challenges to write code for certain error paths for I2C bus drivers because these errors usually don’t happen on the bus. And special I2C bus testers are expensive. In this talk, a new GPIO based driver will be presented which acts on the same bus as the bus master driver under inspection. A live demonstration will be given as well as hints how to handle bugs which might have been found. The scope and limitations of this driver will be discussed. Since it will also be analyzed what actually happens on the wires, this talk also serves as a case study how to snoop busses with only Free Software and OpenHardware (i.e. sigrok).

  • 16:05 – 16:45 – GStreamer for Tiny Devices – Olivier Crête, Collabora

GStreamer is a complete Open Source multimedia framework, and it includes hundreds of plugins, including modern formats like DASH, HLS or the first ever RTSP 2.0 implementation. The whole framework is almost 150MB on my computer, but what if you only have 5 megs of flash available? Is it a viable choice? Yes it is, and I will show you how.

Starting with simple tricks like only including the necessary plugins, all the way to statically compiling only the functions that are actually used to produce the smaller possible footprint.

  • 16:55 – 17:35 – Maintaining a Linux Kernel for 13 Years? You Must be Kidding Me. We Need at Least 30? – Agustin Benito Bethencourt, Codethink Ltd

Industrial grade solutions have a life expectancy of 30+ years. Maintaining a Linux kernel for such a long time in the open has not been done. Many claim that is not sustainable, but corporations that build power plants, railway systems, etc. are willing to tackle this challenge. This talk will describe the work done so far on the kernel maintenance and testing front at the CIP initiative.

During the talk it will be explained how we decide which parts of the kernel to cover – reducing the amount of work to be done and the risk of being unable to maintain the claimed support. The process of reviewing and backporting fixes that might be needed on an older branch will be briefly described. CIP is taking a different approach from many other projects when it comes to testing the kernel. The talk will go over it as well as the coming steps. and the future steps.

Wednesday, October 24

  • 11:05 – 11:45 – HDMI 4k Video: Lessons Learned – Hans Verkuil, Cisco Systems Norway

So you want to support HDMI 4k (3840×2160) video output and/or video capture for your new product? Then this is the presentation for you! I will describe the challenges involved in 4k video from the hardware level, the HDMI protocol level and up to the kernel driver level. Special attention will be given to what to watch out for when buying 4k capable equipment and accessories such as cables and adapters since it is a Wild, Wild West out there.

  • 11:55 – 12:35 – Linux Powered Autonomous Arctic Buoys – Satish Chetty, Hera Systems 

In my talk/presentation, I cover the technical, and design challenges in developing an autonomous Linux powered Arctic buoy. This system is a low cost, COTS based, extreme/harsh environment, autonomous sensor data gathering platform. It measures albedo, weather, water temperature and other parameters. It runs on a custom embedded Linux and is optimized for efficient use of solar & battery power. It uses a variety of low cost, high accuracy/precision sensors and satellite/terrestrial wireless communications.

I talk about using Linux in this embedded environment, and how I address and solve various issues including building a custom kernel, Linux drivers, frame grabbing issues and results from cameras, limited power challenges, clock drifts due to low temperature, summer melt challenges, failure of sensors, intermittent communication issues and various other h/w & s/w challenges.

  • 14:15 – 14:55 – Linux Storage System Bottleneck for eMMC/UFS – Bean Huo & Zoltan Szubbocsev, Micron

The storage device is considered a bottleneck to the system I/O performance. This thinking drives the need for faster storage device interfaces. Commonly used flash based storage interfaces support high throughputs, eg. eMMC 400MB/s, UFS 1GB/s. Traditionally, advanced embedded systems were focusing on CPU and memory speeds and these outpaced advances in storage speed improvements. In this presentation, we explore the parameters that impact I/O performance. We describe at a high level how Linux manages I/O requests coming from user space. Specifically, we look into system performance limitations in the Linux eMMC/UFS subsystem and expose bottlenecks caused by the software through Ftrace. We show existing challenges in getting maximum performance of flash-based high-speed storage device. by this presentation, we want to motivate future optimization work on the existing storage stack.

  • 15:05 – 15:45 – New GPIO Interface for User Space – Bartosz Golaszewski

Since Linux 4.8 the GPIO sysfs interface is deprecated. Due to its many drawbacks and bad design decisions a new user space interface has been implemented in the form of the GPIO character device which is now the preferred method of interaction with GPIOs which can’t otherwise be serviced by a kernel driver. The character device brings in many new interesting features such as: polling for line events, finding GPIO chips and lines by name, changing & reading the values of multiple lines with a single ioctl (one context switch) and many more. In this presentation, Bartosz will showcase the new features of the GPIO UAPI, discuss the current state of libgpiod (user space tools for using the character device) and tell you why it’s beneficial to switch to the new interface.

  • 16:15 – 16:55 – Replace Your Exploit-Ridden Firmware with Linux – Ronald Minnich, Google

With the WikiLeaks release of the vault7 material, the security of the UEFI (Unified Extensible Firmware Interface) firmware used in most PCs and laptops is once again a concern. UEFI is a proprietary and closed-source operating system, with a codebase almost as large as the Linux kernel, that runs when the system is powered on and continues to run after it boots the OS (hence its designation as a “Ring -2 hypervisor”). It is a great place to hide exploits since it never stops running, and these exploits are undetectable by kernels and programs.

Our answer to this is NERF (Non-Extensible Reduced Firmware), an open source software system developed at Google to replace almost all of UEFI firmware with a tiny Linux kernel and initramfs. The initramfs file system contains an init and command line utilities from the u-root project, which are written in the Go language.

  • 17:05 – 17:45 – Unikernelized Real Time Linux & IoT – Tiejun Chen, Vmware

Unikernel is a novel software technology that links an application with OS in the form of a library and packages them into a specialized image that facilitates direct deployment on a hypervisor. But why these existing unikernels have yet to gain large popularity broadly? I’ll talk what challenges Unikernels are facing, and discuss exploration of if-how we could convert Linux as Unikernel, and IoT could be a valuable one of use cases because the feature of smaller size & footprint are good for those resource-strained IoT platforms. Those existing unikernels are not designed to address those IoT characters like power consumption and real time requirement, and they also doesn’t support versatile architectures. Most existing Unikernels just focus on X86/ARM. As a paravirtualized unikenelized Linux, especially Unikernelized Real Time Linux, really makes Unikernels to succeed.

If you’d like to attend the real thing, you’ll need to register and pay a registration fee:

  • Early Registration Fee: US$800 (through August 27, 2017)
  • Standard Registration Fee: US$950 (August 28, 2017 – September 17, 2017)
  • Late Registration Fee: US$1100 (September 18, 2017 – Event)
  • Academic Registration Fee: US$200 (Student/Faculty attendees will be required to show a valid student/faculty ID at registration.)
  • Hobbyist Registration Fee: US$200 (only if you are paying for yourself to attend this event and are currently active in the community)

There’s also another option with the Hall Pass Registration ($150) if you just want to network on visit with sponsors onsite, but do not plan to attend any sessions or keynotes.

TinyFPGA is a Breakout Board for Lattice Semi MachXO2 FPGA

July 24th, 2017 1 comment

We’ve covered several low cost FPGA boards over the years, but if you want a platform with the bare minimum, you may be interested in tinyFPGA breakout board based on Lattice Semi MachXO2 FPGA board that comes with two flavors: A1 with MachXO2-256, and A2 with the more powerful MachXO2-1200 FPGA.

TinyFPGA board specifications:

  • FPGA
    • A1 board – Lattice MachXO2-256 with 256 LUTs, 2 kbits distributed RAM
    • A2 board – Lattice MachXO2-1200 with 1280 LUTs, 10 kbits distributed RAM, 64 kbits EBR SRAM, 64 kbits  flash memory, and a PLL (See datasheet for MachXO2 family)
  • Built-in flash configuration memory programmable via JTAG
  •  I/Os
    • 18 user IOs (21 with JTAGEN)
    • 1x SPI Hard-IP
    • 2x I2C Hard-IPs
    • A2 board only – 1x PLL Hard-IP
  • Power Supply – 3.3V
  • Dimensions – ~3.05 x 1.8 cm

You’ll need a JTAG programmer for Lattice FPGA as well as Lattice Diamond software – available for Windows and Linux – to program the FPGA board. TinyFPGA boards are open source hardware with KiCAD designs released under a GPL v3.0 license.

Click to Enlarge

TinyFPGA A1 and A2 boards are respectively sold for $12 and $18 on Tindie. The board’s designer is also working on TinyFPGA B1 and B2 boards based on ICE40 FPGAs that come with more logic cells and memory, support Project ICEStorm open source tool, and can be programmed via USB without a JTAG programmer.

MYiR Introduces Z-Turn Lite Board Powered by Xilinx Zynq-7007S/Zynq-7010 SoC for $69 and Up

July 20th, 2017 9 comments

Xilinx launched a cost down version of their Zynq-7000 series with Zynq-7000S series SoC combining a single ARM Cortex A9 core with Artix FPGA fabric last year. We’ve already seen sub 100 Euros/Dollars board based on the new SoCs with ZynqBerry and MiniZed boards. MYiR Tech has now launched their own version, a cost-down version of their Z-Turn board, with Z-Turn Lite board featuring either the new cost-down Zynq-7007S or the “good old” Zynq-7010 SoC.

Z-Turn Lite specifications:

  • SoC
    • Xilinx XC7Z007S-1CLG400C (Zynq-7007S) with a single ARM Cortex A9 core @ 667 MHz, Artix-7 FPGA fabric with with 23K logic cells, 14,400 LUTs, 66 DSP slices OR
    • Xilinx XC7Z010-1CLG400C (Zynq-7010) with two ARM Cortex A9 cores @ 667 MHz, Artix-7 FPGA fabric with 28K logic cells, 17,600 LUTs, 80 DSP slices.
  • System Memory – 512 MB DDR3 SDRAM (2 x 256MB, 32-bit)
  • Storage – 4GB eMMC flash, 16MB QSPI flash, and a micro SD slot
  • Connectivity – 10/100/1000M Ethernet
  • USB – 1x mini USB 2.0 OTG port
  • Debugging – USB-UART debug interface, 14-pin JTAG interface
  • User I/O –1x 0.5mm pitch 120-pin connector for expansion interface on the bottom of the board
  • Sensors – 3-axis acceleration sensor and temperature sensor
  • Misc – 2x buttons (reset and user), boot selection jumpers, 5x LEDs, 1x Buzzer
  • Power – 5V/2A  via power barrel
  • Dimensions – 91 x 63 mm (10-layer PCB design)

Compare to Z-Turn, Z-Turn Lite comes with less memory (512MB vs 1GB), adds a 4GB eMMC flash, and removed HDMI, CAN bus, and motion / temperature sensors, and only comes with one expansion interface instead to two. Z-Turn Lite board runs Linux 3.15.0, and the company provides all drivers with source code, Sourcery GCC 6.1 toolchain, and a ramdisk image. Potential target applications include Zynq-7000S series evaluation, multi-axis motor control, machine vision, programmable logic controller (PLC), industrial automation, and test & measurement.

Z-Turn Lite board will start shipping on August 11st, but the company is already taking pre-order for $69 for the Zynq-Z7007S version, and $75 with Zynq-7010, including a 4GB SD card and product disk with documentation and source code. Alternatively, you can also get more complete kit with power supply, and cables for $89 and up. You’ll find purchase link and some hardware documentation like the PDF schematics on the product page.

IceZero Lattice iCE40 FPGA Board is Designed for Raspberry Pi Zero

June 24th, 2017 4 comments

Yesterday, we reported about Olimex’s open source hardware iCE40HX8K-EVB board with a Lattice iCE40 (HX8K) FPGA, and today, another iCE40 FPGA board, also open source hardware, appeared in my news feed with Trenz Electronic’s IceZero board specifically designed to be programmed using a Raspberry Pi Zero board.

Click to Enlarge

IceZero board specifications:

  • FPGA – Lattice ICE40HX4K with 3520 logic gates, and 80 Kbit memory
  • Storage – SPI Flash for FPGA self-configuration
  • Misc – 3x User LEDs;  User Clock: 100 MHz
  • Expansion – 4x unpopulated PMOD Connectors; 40-pin Raspberry Pi female header
  • Dimensions – 56 x 30.5mm (Raspberry Pi HAT Compatible)

The board is supported by icoTC open source FPGA toolchain for Windows and Linux, which you can use in Raspberry Pi Zero (W), and other RPi board with a 40-pin header running Raspbian, as explained in that simple example in Github. Trenz electronic only shared part of the documentation, but you’ll find everything on a blog post on Black Mesa Labs with the design files licensed with the CERN Open Hardware License v1.2, and more technical details about the board.

Block Diagram with Raspberry Pi

Trenz Electronic sells IceZero board for 34 Euros excluding VAT and shipping, but in case you’d like to make it yourself, you can also order the bare PCB on OSH Park.

Olimex Introduces 40 Euros iCE40HX8K-EVB Board with Lattice ICE40 FPGA

June 23rd, 2017 No comments

Last year, Olimex launched their first FPGA board with iCE40HX1K-EVB. The board is very cheap at 22 Euros, but what you can do with it is limited since it only comes with 1280 logic cells. The company has now introduced an upgraded model called iCE40HX8K-EVB with 7680 logic cells, and more I/O headers.

Olimex iCE40HX8K-EVB specifications:

  • FPGA – Lattice Semi iCE40HX8K-CT256 FPGA with 7680 logic gates, 960 Logic Array Blocks, and 128 Kbit memory
  • System Memory – 256Kx16 SRAM (512KB SRAM)
  • Storage – 2MB serial flash
  • Expansion
    • 34-pin connector to access FPGA I/Os
    • 4x 40 pin connectors for GPIOs
  • Debugging / Programming – 10-pin “PGM” connector
  • Misc – 2x user buttons, reset button, 2x user LEDs, power & programming status LEDs
  • Power Supply – 5V via power jack
  • Dimensions – 67×65 cm

The board is open source hardware with the KiCAD schematics and PCB layout, BoM, and Gerber files available on Github. Lattice IceCube2 or Project IceStorm can be used to program the board. So that means we have an open source FPGA board designed with an open source CAD software (KiCAD), and programmable in Verilog with an open source tool (Project IceStorm).

iCE0-ADC Board

You can use the 34-pin connector to connect add-on boards such as:

  • iCE40-ADC with 100Mhz ADC
  • iCE40-DAC with 100Mhz DAC
  • iCE40-IO with VGA, PS2 and IrDA transceiver
  • MOD-DIO with logic analyzer level shifter with programmable 1.5-5.5V threshold.

The modules can be daisy chained with up to 4x DAC and 4x ADC modules.

Olimex iCE40HX8K-EVB can be purchased for 39.95 Euros on Olimex store, where you’ll also find the aforementioned add-on boards for 9.95 to 15.95 Euros.

$89 MiniZed Development Board based on Xilinx Zynq Z-7007S SoC Includes WiFi, Bluetooth, Arduino Headers

June 14th, 2017 6 comments

Avnet has unveiled MiniZed development board – part of ZedBoard family – powered by a Xilinx Zynq Z-7007s SoC with an ARM Cortex A9 processor and FPGA fabric,  supporting WiFi and Bluetooth connectivity, and equipped with Arduino and PMOD headers.

MiniZed board (AES-MINIZED-7Z007-G) specifications:

  • SoC – Xilinx Zynq-7007S single ARM Cortex A9 processor up to 677 MHz + FPGA with 23K logic cells, 1.8 Mb block RAM, 60 DSP slices
  • System Memory – 512 MB DDR3L
  • Storage –  8 GB eMMC flash, 128 Mbit QSPI flash
  • Connectivity –  Wi-Fi 802.11b/g/n and Bluetooth 4.1 plus EDR and BLE  via Murata “Type 1DX” wireless module
  • USB – 1x USB 2.0 host port
  • Sensors – 3-axis accelerator and temperature sensor (LIS2DS12);  Digital Microphone (MP34DT05)
  • Expansion Interfaces:
    • 2x Pmod compatible connectors with 16x GPIOs
    • Arduino UNO R3 compatible header with 22x GPIOs
  • Debugging –  JTAG and serial console via micro USB port
  • Misc – 2x bi-element user LEDs, user & reset push buttons; user switch
  • Power Supply – 5V via micro USB port

The company provides bare-metal code samples, as well as Xilinux PetaLinux for the board. You’ll find hardware and software documentation, including BoM, schematics, and getting started guides on the documentation page.


Click to Enlarge

MiniZed is the cheapest Zedboard so far, which makes it ideal as a training, prototyping and proof-of-concept demo platform, and it can be used to showcase wireless designs using Wi-Fi and Bluetooth, audio signal processing examples with the MIC input, as well as IoT & cloud demos using external and on-board sensors.

MiniZed can be purchased for $89 on Avnet with the company mentioning that the retail price may be higher in Asia, Australia, New Zealand and Japan. You may find further info on’s MiniZed page.

Intel DLIA is a PCIe Card Powered by Aria 10 FPGA for Deep Learning Applications

May 29th, 2017 No comments

Intel has just launched their DLIA (Deep Learning Inference Accelerator) PCIe card powered by Intel Aria 10 FPGA, aiming at accelerating CNN (convolutional neural network) workloads such as image recognition and more, and lowering power consumption.

Some of Intel DLIA hardware specifications:

  • FPGA – Intel (previously Altera) Aria 10 FPGA @ 275 MHz delivering up to 1.5 TFLOPS
  • System Memory – 2 banks 4G 64-bit DDR4
  • PCIe – Gen3 x16 host interface; x8 electrical; x16 power & mechanical
  • Form Factor – Full-length, full-height, single wide PCIe card
  • Operating Temperature – 0 to 85 °C
  • TDP – 50-75Watts hence the two cooling fans

The card is supported in CentOS 7.2, and relies on Intel Caffe framework, Math Kernel library for Deep Neural Networks (MKL-DNN), and works with various network topologies (AlexNet, GoogleNet, CaffeNet, LeNet, VGG-16, SqueezeNet…). The FPGA is pre-programmed with Intel Deep Learning Accelerator IP (DLA IP).

Intel DLIA can be used by cloud services providers to filter content, track product photos, for surveillance and security applications for example for face recognition and license plate detection, in the factory to detect defects automatically, and in retail stores to track foot traffic, and monitor inventory.

You’ll find more details including links to get started and the SDK in the product page.