JEDEC first introduced UFS 3.0 embedded flash in September 2017 with promises of 2.4GB/s transfer rates, and somehow this was bumped to 2.9GB/s (23.2 Gbps) when UFS 3.0 specification was published in January 2018.
JEDEC has now published UFS 3.1 specification with the same theoretical performance, but some new features that should improve write performance, random read performance, as well as lower power consumption and costs.
Precisely two documents are now available for purchase, unless you work for a JEDEC member, in which case those are free downloads:
- The Universal Flash Storage (UFS) version 3.1, JESD220E.
- An optional new companion standard, JESD220-3: UFS Host Performance Booster (HPB) Extension.
The first defines three main improvements as part of UFS 3.1:
- Write Booster – an SLC non-volatile cache that amplifies write speed
- DeepSleep – a new UFS device low power state targeting lower-cost systems that share UFS voltage regulators with other functions
- Performance Throttling Notification – allows the UFS device to notify the host when storage performance is throttled due to high temperature.
Beside just saving power, DeepSleep also promises to lower overall devices cost since the power circuitry can be made simpler.
The second document explains how UFS 3.1 embedded flash devices could optionally cache the UFS device logical-to-physical address map in the system’s DRAM in order to provide larger and faster caching thereby improving the (random) read performance of the device.