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Category: SiFive

Posted on by Jean-Luc Aufranc (CNXSoft) - 5 Comments on Linux 6.16 Release – Main changes, Arm, RISC-V, and MIPS architectures

Linux 6.16 Release – Main changes, Arm, RISC-V, and MIPS architectures

Linux 6.16 release arm linux mips

Linus Torvalds has just announced the release of Linux 6.16 on LKML: It’s Sunday afternoon, and the release cycle has come to an end. Last week was nice and calm, and there were no big show-stopper surprises to keep us from the regular schedule, so I’ve tagged and pushed out 6.16 as planned. It’s worth noting that the upcoming merge window for 6.17 is going to be slightly chaotic for me: I have multiple family events this August (a wedding and a big birthday), and with said family being spread not only across the US, but in Finland too, I’m spending about half the month traveling. That means that I will try very hard to get most of the merge window done the first week before my travels start, and I already ended upgiving a heads-up on that to the people who tend to send me the most pull requests. […]

Posted on by Jean-Luc Aufranc (CNXSoft) - No Comments on Linux 6.15 Release – Main changes, Arm, RISC-V and MIPS architectures

Linux 6.15 Release – Main changes, Arm, RISC-V and MIPS architectures

Linux 6.15 release

Linus Torvalds has just announced the release of Linux 6.15: So this was delayed by a couple of hours because of a last-minute bug report resulting in one new feature being disabled at the eleventh hour, but 6.15 is out there now. Apart from that final scramble, things looked pretty normal last week. Various random small fixes all over, with drivers as usual accounting for most of it. But we’ve got some bcachefs fixes, some core networking, and some mm fixes in there too. Nothing looks particularly scary. And this obviously means that the merge window opens tomorrow as usual, and I see the usual people being proactive and having sent me their pull requests. It’s memorial day tomorrow here in the US, but like the USPS, “neither snow nor rain nor heat nor gloom of night” – nor memorial day – stops the merge window. [ Actually, thinking back […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 4 Comments on DC-ROMA RISC-V Mainboard is designed for the Framework Laptop 13 modular laptop

DC-ROMA RISC-V Mainboard is designed for the Framework Laptop 13 modular laptop

DeepComputing DC ROMA RISC V mainboard

DeepComputing’s DC-ROMA RISC-V Mainboard is designed for the modular Framework Laptop 13 and powered by a StarFive JH7110 quad-core RISC-V processor running either Ubuntu 24.04 Desktop or Fedora 41 Linux distribution. The Framework Laptop 13 was initially offered with Intel Core i5-1135G7, Core i7-1165G7, or Core i7-1185G7 processor, but the advantage of a modular laptop is that you can replace components, and that’s exactly what the “DC-ROMA RISC-V Mainboard” does by allowing users/developers to do by switching to a less powerful RISC-V processor for software development. Framework Laptop 13 specifications with DC-ROMA RISC-V Mainboard: SoC – StarFive JH7110 CPU Quad-core 64-bit RISC-V SiFive U74 (RV64GC) processor @ up to 1.5 GHz with 32KB D-Cache, 32KB I-cache Single-core 64-bit RISC-V SiFive S7 (RV64IMAC) monitor core with 16KB I-cache, 8KB DTIM Single-core 32-bit RISC-V SiFive E24 (RV32IMFC) real-time control core with 16KB I-cache Up to 2MB L2 cache GPU – Imagination BXE-4-32 […]

Posted on by Jean-Luc Aufranc (CNXSoft) - No Comments on HiFive Premier P550 mini-DTX motherboard features ESWIN EIC7700X RISC-V AI SoC, up to 32GB DDR5, a PCIe x16 slot

HiFive Premier P550 mini-DTX motherboard features ESWIN EIC7700X RISC-V AI SoC, up to 32GB DDR5, a PCIe x16 slot

SiFive HiFive Premier P550 RISC-V mini-DTX motherboard

SiFive HiFive Premier P550 is a mini-DTX (203 x 170mm) motherboard powered by a 1.4 GHz ESWIN EIC7700X quad-core RISC-V SiFive P550 SoC with up to 19.95 TOPS of AI performance, and equipped with up to 32GB LPDDR5 memory and a 128GB eMMC flash all soldered on a system-on-module. The motherboard itself features a SATA III connector for data storage, includes an HDMI 2.0 port for 4K video output, a PCIe Gen3 x16 slot (working at x4), two gigabit Ethernet ports, an M.2 Key-E socket to add a WiFi/Bluetooth card, up to five USB interfaces, and more. HiFive Premier P550 specifications: SoC – ESWIN EIC7700X CPU 4x SiFive Performance P550 RV64GC RISC-V cores @ 1.4GHz (up to 1.8GHz when overclocked) with Cortex-A75-class performance 32KB(I) + 32KB(D) L1 Cache 256KB L2 Cache 4MB shared L3 Cache Cache supports ECC (support SECDED) NPU (Not currently supported in software) – Up to 19.95 […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 11 Comments on Microchip PIC64GX is a quad-core 64-bit RISC-V microprocessor for real-time processing

Microchip PIC64GX is a quad-core 64-bit RISC-V microprocessor for real-time processing

Microchip PIC64GX

Microchip has introduced its first 64-bit RISC-V microprocessor family with the PIC64GX pin-to-pin compatible with the company’s PolarFire SoC FPGA devices and designed for edge designs for the industrial, automotive, communications, IoT, aerospace, and defense segments. The PIC6GX MPU supports asymmetric multiprocessing (AMP) to run Linux, real-time operating systems, and bare metal in a single processor cluster with secure boot capabilities. The company further claims the PIC64GX MPU is “the first RISC-V multi-core solution that is AMP capable for mixed-criticality systems”. The first member of the PIC64GX RISC-V family is the PIC64GX1000 microprocessor. Microchip PIC64GX1000 specifications: CPU Quad-core SiFive U54 64-bit five-stage, single-issue, in-order pipeline RISC-V (RV64GC) processor at up to 625 MHz with AMP and deterministic latencies, PMP and MMU units Single-core SiFive E51 64-bit RISC-V (RV64IMAC) monitor processor core at up to 625 MHZ with PMP unit Cache L1 memory subsystem with Single-Error Correct, Double-Error Detect (SECDED) Flexible […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 6 Comments on SiFive announces Essential Gen4 RISC-V CPUs for embedded applications

SiFive announces Essential Gen4 RISC-V CPUs for embedded applications

SiFive Essential Gen4 RISC-V CPU IP

As the RISC-V Summit Europe 2024 is underway, SiFive has announced the fourth generation of its “Essential” RISC-V CPUs (Essential Gen4) with improved power efficiency and more flexible interfaces for SoCs used in embedded devices. The update covers 32-bit and 64-bit RISC-V cores including the U6 and U7-series 64-bit application processors, the S2, S6, and S7 64-bit real-time embedded processors, and the E2, E6, and E7 32-bit real-time embedded processors. Essential Gen4 IP keys features: Up to 40% runtime power reduction 8x different baseline embedded 32-bit and 64-bit cores From 2-stage single-issue to 8-stage superscalar Improved L2 cache and enhanced L1 memory Configuration and integration options CPU type, profile, and options On-chip memories selection System, peripheral, and front ports Advanced power management and security Debug and trace Software support includes embedded Linux and FreeRTOS operating systems and Eclipse-based IDE for C/C++ development. That’s another low-quality, light-on technical details announcement from […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 2 Comments on Linux 6.9 release – Main changes, Arm, RISC-V, and MIPS architectures

Linux 6.9 release – Main changes, Arm, RISC-V, and MIPS architectures

Linux 6.9 release

Linus Torvalds has just announced the release of Linux 6.9 on LKML: So Thorsten is still reporting a few regression fixes that haven’t made it to me yet, but none of them look big or worrisome enough to delay the release for another week. We’ll have to backport them when they get resolved and hit upstream. So 6.9 is now out, and last week has looked quite stable (and the whole release has felt pretty normal). Below is the shortlog for the last week, with the changes mostly being dominated by some driver updates (gpu and networking being the big ones, but “big” is still pretty small, and there’s various other driver noise in there too). Outside of drivers, it’s some filesystem fixes (bcachefs still stands out, but ksmbd shows up too), some late selftest fixes, and some core networking fixes. And I now have a more powerful arm64 machine […]

Posted on by Jean-Luc Aufranc (CNXSoft) - No Comments on Linux 6.7 release – Main changes, Arm, RISC-V, and MIPS architectures

Linux 6.7 release – Main changes, Arm, RISC-V, and MIPS architectures

Linux 6.7 release

Linus Torvalds has just announced the release of Linux 6.7, following Linux 6.6 LTS a little over two months ago: So we had a little bit more going on last week compared to the holiday week before that, but certainly not enough to make me think we’d want to delay this any further. End result: 6.7 is (in number of commits: over 17k non-merge commits, with 1k+ merges) one of the largest kernel releases we’ve ever had, but the extra rc8 week was purely due to timing with the holidays, not about any difficulties with the larger release. The main changes this last week were a few DRM updates (mainly fixes for new hw enablement in this version – both amd and nouveau), some more bcachefs fixes (and bcachefs is obviously new to 6.7 and one of the reasons for the large number of commits), and then a few random […]