SiFive Category - Page 2 of 7 - CNX Software

October 10, 2022 by Jean-Luc Aufranc (CNXSoft) - 12 Comments

Intel Horse Creek platform showcased with SiFive P550 RISC-V CPU, 8GB DDR5, PCIe Gen5

When SiFive introduced its Performance P550 64-bit RISC-V processor in 2021, we were told that Intel would use it in the Horse Creek platform with “leading-edge interface IP such as DDR and PCIe” and manufactured with Intel’s 7nm process. We now have more details about the Horse Creek platform, as a development board was showcased for the first time in public at the Intel Innovation 2022 Developer Conference, and according to a report by Wikichip, the Cortex-A75 class quad-core RISC-V processor runs at up to 2.2 GHz, supports DDR5-5600 memory and eight PCIe 5.0 lanes, and was taped out with Intel 4 process. Horse Creek platform specifications: CPU – SiFive P500 quad-core RISC-V processor @ up to 2.2 GHz with a 13-stage, 3-issue, out-of-order (OoO) pipeline, private L2 cache, and common L3 cache Memory – DDR5-5600 interface PCIe – PCIe Gen5 through Intel’s PCIe PHY with 8 lanes, Synopsys PCIe […]

October 3, 2022October 3, 2022 by Jean-Luc Aufranc (CNXSoft) - 3 Comments

Linux 6.0 release – Main changes, Arm, RISC-V, and MIPS architectures

Linux 6.0 has just been released by Linus Torvalds: So, as is hopefully clear to everybody, the major version number change is more about me running out of fingers and toes than it is about any big fundamental changes. But of course there’s a lot of various changes in 6.0 – we’ve got over 15k non-merge commits in there in total, after all, and as such 6.0 is one of the bigger releases at least in numbers of commits in a while. The shortlog of changes below is only the last week since 6.0-rc7. A little bit of everything, although the diffstat is dominated by drm (mostly amd new chip support) and networking drivers. And this obviously means that tomorrow I’ll open the merge window for 6.1. Which – unlike 6.0 – has a number of fairly core new things lined up. But for now, please do give this most […]

September 16, 2022September 16, 2022 by Jean-Luc Aufranc (CNXSoft) - 1 Comment

SiFive unveils Automotive E6-A, X280-A, and S7-A RISC-V processors

RISC-V is coming to your car too, with the introduction of SiFive Automotive E6-A, X280-A, and S7-A RISC-V processors designed for automotive applications such as infotainment, cockpit, connectivity, ADAS, and electrification. Those are built on the existing SiFive Essential 6-series E6 32-bit real-time cores, SiFive Intelligence X280 64-bit RISC-V processor with AI extensions, and SiFive S7 64-bit real-time cores (equivalent to Cortex-R7/R8), but adds safety, security, and performance required by the automotive market such as ASIL compliance. Each new core targets specific applications within a vehicle: The SiFive E6-A series will be found in system control boards, hardware security modules (HSMs) and safety islands, as well as standalone in microcontrollers. The SiFive S7-A 64-bit real-time core is said to be suited to the needs of SoCs with performant safety islands, requiring both low latency interrupt support and the same 64-bit memory space as the main application CPUs. The SiFive X280-A […]

May 23, 2022 by Jean-Luc Aufranc (CNXSoft) - 1 Comment

Linux 5.18 release – Main changes, Arm, RISC-V, and MIPS architectures

Linux 5.18 is out! Linus Torvalds has just announced the release on lkml: No unexpected nasty surprises this last week, so here we go with the 5.18 release right on schedule. That obviously means that the merge window for 5.19 will open tomorrow, and I already have a few pull requests pending. Thank you everybody. I’d still like people to run boring old plain 5.18 just to check, before we start with the excitement of all the new features for the merge window. The full shortlog for the last week is below, and nothing really odd stands out. The diffstat looks a bit funny – unusually we have parsic architecture patches being a big part of it due to some last-minute cache flushing fixes, but that is probably more indicative of everything else being pretty small. So outside of the parisc fixes, there’s random driver updates (mellanox mlx5 stands out, […]

May 17, 2022October 21, 2022 by Jean-Luc Aufranc (CNXSoft) - 10 Comments

Ubuntu Kylin 20.04 OS works on RISC-V hardware

China-developed Ubuntu Kylin 20.04 is now supporting RISC-V architecture with an image for HiFive Unmatched mini-ITX motherboard, and work will be done on an unnamed Starfive SBC that should be the VisionFive board with a GPUless JH7100 dual-core RISC-V SoC or an upgraded version with JH7110 SoC featuring an Imagination IMG BXE-4-32 GPU. You may have read recent reports about China asking government entities, including state-owned enterprises (SOE), to replace foreign hardware and software within a two-year period. So that means avoiding systems based on Intel and AMD processors, so working on RISC-V open architecture makes perfect sense, since over time, Chinese manufacturers should be able to make RISC-V SoCs and PCs based on those processors, albeit probably not within the next two years at any significant scale. Ubuntu Kylin 20.04 RISC-V, as well as the newly released Ubuntu Kylin 22.04 x86, can be found on the English download page […]

March 21, 2022March 22, 2022 by Jean-Luc Aufranc (CNXSoft) - No Comments

Linux 5.17 release – Main changes, Arm, RISC-V, and MIPS architectures

Linus Torvalds has just released Linux 5.17: So we had an extra week of at the end of this release cycle, and I’m happy to report that it was very calm indeed. We could probably have skipped it with not a lot of downside, but we did get a few last-minute reverts and fixes in and avoid some brown-paper bugs that would otherwise have been stable fodder, so it’s all good. And that calm last week can very much be seen from the appended shortlog – there really aren’t a lot of commits in here, and it’s all pretty small. Most of it is in drivers (net, usb, drm), with some core networking, and some tooling updates too. It really is small enough that you can just scroll through the details below, and the one-liner summaries will give a good flavor of what happened last week. Of course, this means […]

February 8, 2022February 9, 2023 by Jean-Luc Aufranc (CNXSoft) - 16 Comments

Intel to invest $1 billion in foundry innovation, becomes RISC-V International member

Intel has just announced a $1 billion fund to support companies bringing innovations and new technologies to the foundry ecosystem. The company says the fund will prioritize investments in “capabilities that accelerate foundry customers’ time to market – spanning intellectual property (IP), software tools, innovative chip architectures, and advanced packaging technologies.” What’s interesting is that it does not only cover x86 architecture but also Arm and RISC-V, with a focus on the latter, as Intel has just become a Premier member of RISC-V International, and partnered with several companies offering RISC-V solutions including Andes Technology, Esperanto Technologies, SiFive, and Ventana Micro Systems. Intel’s Open Chiplet Platform Part of the investment will go to the Open Chiplet Platform offering a modular approach to chip design through chiplets with each block/chiplet customized for a particular function. This will allow designers to select the best IP and process technologies for a particular SoC. […]

January 10, 2022February 1, 2022 by Jean-Luc Aufranc (CNXSoft) - No Comments

Linux 5.16 Release – Main Changes, Arm, RISC-V and MIPS architectures

Linus Torvalds has just announced the release of Linux 5.16: Not a lot here since -rc8, which is not unexpected. We had that extra week due to the holidays, and it’s not like we had lots of last-minute things that needed to be sorted out. So this mainly contains some driver fixes (mainly networking and rdma), a cgroup credential use fix, a few core networking fixes, a couple of last-minute reverts, and some other random noise. The appended shortlog is so small that you might as well scroll through it. This obviously means that the merge window for 5.17 opens tomorrow, and I’m happy to say I already have several pending early pull requests. I wish I had even more, because this merge window is going to be somewhat painful due to unfortunate travel for family reasons. So I’ll be doing most of it on the road on a laptop […]