CSEM and USJC together have developed an ultra-low-power RISC-V chip for electronic gadgets such as wearables. The semiconductor companies, from Switzerland and Japan respectively, have been in the market for a while, developing technologies for low-power chips. Their latest collaboration uses Adaptive Body Biasing (ABB) and Deeply Depleted Channel (DDC) to build an ultra-low-power RISC-V chip with all the required and necessary components. Originating from the labs of CSEM, the Adaptive Body Biasing dwells into the operating efficiency of all the modes of ON, Standby, and OFF. There has been the problem of power leakage in Standby and OFF operating modes, but the Adaptive Body Biasing technology helps design to minimize power leakage when the processor is not operating while keeping the best performance in ON mode. For most of the designs, the processor is in Standby mode waiting for the incoming data or the next event to be offered. […]
Ultra-Low-Power RISC-V System-on-Chip features Adaptive Body Biasing Technology
