mips News - Page 3 of 19 - CNX Software

October 27, 2022October 27, 2022 by Jean-Luc Aufranc (CNXSoft) - 2 Comments

WiFi HaLow IoT gateway is based on Morse Micro MM6108 802.11ah chip

Most WiFi HaLow hardware platforms we’ve seen so far are based on Newracom chips, but AsiaRF AP7688-WHM WiFi HaLow IoT gateway features a module based on Morse Micro MM6108 802.11ah SoC instead. The gateway is powered by a 580 MHz MediaTek MT7688 MIPS processor providing 802.11n WiFi 4 and dual Ethernet networking, and features a USB port as well as an RS232 console for industrial control. WiFi HaLow (802.11ah) enables video and data transmission at a range of up to one kilometer and data rates of up to 32.5 Mbps. AP7688-WHM WiFi HaLow gateway specifications: SoC – Mediatek MT7688 MIPS SoC @ 580 MHz with built-in WiFi 4 System Memory – TBD Storage – TBD Connectivity 2x Ethernet RJ45 ports 2.4 GHz WiFi 4 1T1R up to 150 Mbps; PCB antenna 850 to 950 MHz WiFi HaLow 1T1R up to 32.5Mbps @ 8 MHz bandwidth via Morse Micro MM6108 chip; […]

October 3, 2022October 3, 2022 by Jean-Luc Aufranc (CNXSoft) - 3 Comments

Linux 6.0 release – Main changes, Arm, RISC-V, and MIPS architectures

Linux 6.0 has just been released by Linus Torvalds: So, as is hopefully clear to everybody, the major version number change is more about me running out of fingers and toes than it is about any big fundamental changes. But of course there’s a lot of various changes in 6.0 – we’ve got over 15k non-merge commits in there in total, after all, and as such 6.0 is one of the bigger releases at least in numbers of commits in a while. The shortlog of changes below is only the last week since 6.0-rc7. A little bit of everything, although the diffstat is dominated by drm (mostly amd new chip support) and networking drivers. And this obviously means that tomorrow I’ll open the merge window for 6.1. Which – unlike 6.0 – has a number of fairly core new things lined up. But for now, please do give this most […]

August 1, 2022August 1, 2022 by Jean-Luc Aufranc (CNXSoft) - 14 Comments

Linux 5.19 Release – Main changes, Arm, RISC-V and MIPS architectures

Linus Torvalds has just announced the release of Linux 5.19. It should be the last 5.xx version, with Linux 6.0 coming for the next cycle: So here we are, one week late, and 5.19 is tagged and pushed out. The full shortlog (just from rc8, obviously not all of 5.19) is below, but I can happily report that there is nothing really interesting in there. A lot of random small stuff. In the diffstat, the loongarch updates stand out, as does another batch of the networking sysctl READ_ONCE() annotations to make some of the data race checker code happy. Other than that it’s really just a mixed bag of various odds and ends. On a personal note, the most interesting part here is that I did the release (and am writing this) on an arm64 laptop. It’s something I’ve been waiting for for a _loong_ time, and it’s finally reality, […]

June 6, 2022June 6, 2022 by Jean-Luc Aufranc (CNXSoft) - 12 Comments

X1501 Pico SoM – MIPS, Linux in a 16x16mm module

We’ve just written about the Notkia phone repurposing Nokia 168x phones with a new PCB featuring an Ingenic X1000E MIPS processor running mainline Linux, but it turns out the developer (Reimu NotMoe, CTO of SudoMaker) has also designed the X1501 Pico SoM, a tiny 16×16 system-on-module equipped with Ingenic X1501 MIPS system-in-package (SiP). The module can be that small because the single-core 1GHz Ingenic 1501 SiP embeds 8MB LPDDR, as well as apparently a 16Mbit NOR flash that stores stripped-down versions of U-boot and the Linux kernel, plus a minimal, busybox-based rootfs. X1501 Pico system-on-module specifications: SoC – Ingenic X1501 MIPS32r2 processor @ 1GHz, a MIPSr2 real-time core @ 300 MHz (not shown in datasheet), 8MB LPDDR and 16KB tightly coupled SRAM, 16Mbit NOR flash Castellated holes with USB 2.0 OTG, I2C, SPI, SDIO and DVP, analog mono audio output & digital microphone input EFUSE based Secure Boot Power Management […]

June 3, 2022June 7, 2022 by Jean-Luc Aufranc (CNXSoft) - 6 Comments

Nokia 1680 phone gets new PCB with MIPS SoC, runs mainline Linux

Reimu NotMoe has designed the “Notkia” PCB based on Ingenic X1000E MIPS processor with 64MB built-in RAM and following the exact same dimensions as the PCB found in Nokia 168x phones (1680, 1681, 1682), and allowing the phone to run mainline Linux. The board also comes with 32MB NOR flash, a 4GB SLC NAND flash, and supports LoRa, 2.4 GHz WiFi, Bluetooth, and GNSS connectivity, but no cellular modem. Combining Nokia 168x phone with Notkia PCBA creates a phone with the following specifications: SoC – Ingenic X1000E single-core XBurst MIPS processor @ 1.0 GHz (2200+ CoreMark) with 64MB RAM Storage – 32MB NOR flash + 4GB SLC NAND flash Display – 2.0-inch 240×320 IPS LCD, 3/4 visible (Replaces the original 128×160 TFT screen in the phone) Camera – 5MP camera with auto focus (only available in the Nokia 1680 case) Audio – Yamaha MA-3 (YMU762) music synthesizer and regular I2S […]

May 23, 2022 by Jean-Luc Aufranc (CNXSoft) - 1 Comment

Linux 5.18 release – Main changes, Arm, RISC-V, and MIPS architectures

Linux 5.18 is out! Linus Torvalds has just announced the release on lkml: No unexpected nasty surprises this last week, so here we go with the 5.18 release right on schedule. That obviously means that the merge window for 5.19 will open tomorrow, and I already have a few pull requests pending. Thank you everybody. I’d still like people to run boring old plain 5.18 just to check, before we start with the excitement of all the new features for the merge window. The full shortlog for the last week is below, and nothing really odd stands out. The diffstat looks a bit funny – unusually we have parsic architecture patches being a big part of it due to some last-minute cache flushing fixes, but that is probably more indicative of everything else being pretty small. So outside of the parisc fixes, there’s random driver updates (mellanox mlx5 stands out, […]

May 11, 2022 by Jean-Luc Aufranc (CNXSoft) - 4 Comments

MIPS unveils RISC-V eVocore P8700 and I8500 multiprocessor IP cores

MIPS is dead, right? Well, there’s now very little done on the architecture itself, MIPS (the company) has decided to switch to RISC-V architecture, and unveiled the eVocore product lineup currently comprised of the eVocore P8700 and I8500 multiprocessor IP cores. The 64-bit cores are scalable from single-core multi-thread to a single cluster with multiple cores, and up to a multi-cluster, and target high-performance, real-time compute applications such as networking, data centers, and automotive. The eVocore P8700 comes with a 16-stage deep pipeline with multi-issue Out-of-Order (OOO) execution and multi-threading. MIPS claims it has single-threaded performance greater than what is currently available in other RISC-V CPU IP offerings, but did not provide any numbers. It will likely be used in the cloud and high-end servers as it can scale up to 64 clusters, 512 cores and 1,024 harts/threads. P8700 highlights: Multi-issue superscalar Out of Order (OOO) with Multi-threading 16-stage pipeline […]

April 7, 2022April 8, 2022 by Jean-Luc Aufranc (CNXSoft) - 2 Comments

AnkerMake M5 3D printer comes with AI camera, prints at up to 300mm/s (Crowdfunding)

Anker is better known for its charger and power banks, but the company has now entered the 3D printer market with the AnkerMake M5 3D printer which is said to print five times faster and comes with an AI camera for monitoring the prints. Besides the up to 300mm/s printing speed, other highlights of the 3D printer include Google Assistant & Amazon Alexa voice assistant compatibility, and easy assembly that requires 3 steps done in about 15 minutes. AnkerMake M5 3D printer specifications: SoC – Ingenic X2000 tri-core MIPS processor with 2x XBurst cores @ 1.2 GHz plus one XBurst0 core @ 240 MHz running Linux MCU – STM32F407 running Marlin firmware Print volume (L x W x H) – 235 × 235 × 250 mm Standard speed – 250 mm/s Speed range – 50 – 300 mm/s Acceleration speed – 2500 mm/s² X-axis movement – 42 – 40 stepper […]