rtos News - Page 6 of 15 - CNX Software

February 5, 2021 by Saumitra Jagdale - 12 Comments

Raspberry Pi Pico Gets supports for Rust, RT-Thread OS and FreeRTOS

Raspberry Pi Pico Rust RT-Thread FreeRTOS

In January end, we saw the launch of Raspberry Pi Pico equipped with an RP2040 dual-core Cortex-M0+ microcontroller working up to 133 MHz with official support for MicroPython and C. In this feature, we will be discussing the Raspberry Pi Pico’s flexible software support compatible with RP2040 MCU, apart from the MicroPython, C/C++, and upcoming Arduino IDE software support. We will specifically be focusing on Rust, RT-Thread OS, and FreeRTOS support for Raspberry Pi Pico. Rust Code Running on Raspberry Pi Pico Rust language is considered fast, reliable, and secure when it comes to IoT gateways. It also opens up the option for writing extremely low-level code, such as operating system kernels or microcontroller applications. Porting Rust with RP2040 for working with Raspberry Pi Pico was seen in Jonathan Pallant’s Twitter Feed. The RP2040 comes with an external QSPI flash. The internal mask-ROM reads the programs from the external flash […]

November 15, 2020November 19, 2020 by Abhishek Jadhav - 3 Comments

LoRa & LoRaWAN support in Zephyr OS

The story of LoRa began in 2009 when Cycleo, a French company, invented LoRa. LoRa (Long Range) support for Zephyr OS goes back to December 2019. Since then, there has been a huge interest among the community to extend their support for it. More recently, LoRaWAN (low-power wide-area network) support was added to Zephyr OS. This will provide true networking support to Zephyr OS over LoRa. It operates in licensed free Sub Gigahertz frequencies (865 MHz-India, 868 MHz-Europe, etc…). It makes the perfect choice for low data rates and long-range applications. What is LoRaWAN? LoRaWAN is a MAC layer that sits on top of the LoRa. According to the OSI model, LoRaWAN is the MAC (media access control) layer while LoRa is the PHY (physical) layer. LoRa protocol is closed, meaning it is proprietary to Semtech, while LoRaWAN specifications are open to the public. The reference implementation is available at […]

October 9, 2020October 9, 2020 by Jean-Luc Aufranc (CNXSoft) - 5 Comments

$16 Banana Pi BPI-EAI80 Cortex-M4F Board Embeds AI Accelerator, WiFi Module

Banana Pi BPI-EAI80 AI MCU Development Board

Last April, we wrote about Edgeless EAI-Series dual Arm Cortex-M4 MCU equipped with a 300 GOPS CNN-NPU for AI at the very edge as we had discovered the chip in an upcoming Banana Pi board. It turns out Banana Pi BPI-EAI80 development board powered by Edgeless EAI80 AI microcontroller has just launched for $16 on Aliexpress, or you could get a complete kit with a touchscreen display, a camera, and a USB power supply for $80. Banana Pi BPI-EAI80 development board specifications: System-in-Package – Edgeless EIA80 dual-core Cortex-M4F microcontroller @ 200MHz with 300GOPS AI accelerator (CNN-NPU), 384KB of SRAM including 256KB for CNN-NPU, and 8MB SDRAM Storage – SPI flash Display I/F – LCD connector up to 1024×768 Camera I/F – 1x DVP camera interface Audio – 2x onboard microphones Connectivity – 2.4GHz 802.11b/g/n WiFI 4 using ESP8266 module USB – 1x USB 2.0 Type-C port Expansion 40-pin GPIO header […]

April 26, 2020April 26, 2020 by Jean-Luc Aufranc (CNXSoft) - 8 Comments

Ingenic T31 AI Video Processor Combines MIPS & RISC-V Cores

Ingenic T31 MIPS & RISC-V Video Processor

Last week we asked “is MIPS dead?” question following the news that Wave Computing had filed for bankruptcy, two MIPS Linux maintainers had left, and China-based CIP United now obtained the exclusive MIPS license rights for mainland China, Hong Kong, and Macau. Ingenic is one of those Chinese companies that have offered MIPS-based processors for several years, but one commenter noted that Ingenic joined the RISC-V foundation, and as a result, we could speculate the company might soon launch RISC-V processors, potentially replacing their MIPS offerings. But Ingenic T31 video processor just features both with a traditional Xburst MIPS Core combines with a RISC-V “Lite” core Ingenic T31 specifications: Processors XBurst 1 32-bit MIPS core clocked at 1.5GHz with Vector Deep Learning accelerator based on SIMD128, 64KB + 128KB L1/L2 Cache RISC-V independent lite core System Memory – Built-in 512Mbit (64MB) or 1Gbit (128MB) DDR2 Storage – Quad SPI flash, […]

February 25, 2020February 25, 2020 by Jean-Luc Aufranc (CNXSoft) - 9 Comments

Getting Started with RT-Thread Nano RTOS on RISC-V Processors

CNXSoft: This is a guest post by RT-Thread explaining how to create your first program running on their real-time operating system using a GD32V RISC-V MCU board as an example. This article describes how to “port” RT-Thread Nano to the RISC-V architecture, using the Eclipse IDE, GCC toolchain, and a basic project for the Gigadevice GD32V103 MCU. Foreword RT-Thread is an open-source embedded real-time operating system. RT-Thread has a standard version and a Nano version. The standard version consists of a kernel layer, components and service layer, and IoT framework layer, while the Nano version has a very small footprint and refined hard real-time kernel, better suited to resource-constrained microcontroller units (MCU). The main steps for porting Nano are as follows: Prepare a basic Eclipse project and get the RT-Thread Nano source code. Add the RT-Thread Nano source code to the base project and add the corresponding header path. Modify […]

February 24, 2020February 24, 2020 by Jean-Luc Aufranc (CNXSoft) - No Comments

Google Summer of Code 2020 Mentoring Organizations Announced

Every year Google organizes the Summer of Code inviting students to work on open-source projects and even get paid for it. The company first select mentoring organizations, before accepting applications from students. Google has now announced the 200 organizations/projects that have been selected for Summer of Code 2020. Many projects are higher-level software development such as web development or desktop programs development but there are also projects closer to the hardware-side of things with operating systems and multimedia projects. Some interesting organization and/or projects part of the audio / graphics / video / multimedia category include: apertus Association developing AXIOM open-source hardware camera FFmpeg multimedia framework to decode, encode, transcode, de/mux, stream, filter & play audio and video stream found in many projects OpenCV Open Source Computer Vision Library for computer vision and deep learning applications. XOrg foundation for X Window System and related projects such as Mesa, DRI, Wayland, […]

December 11, 2019July 5, 2020 by Jean-Luc Aufranc (CNXSoft) - 3 Comments

RISC-V based PolarFire SoC FPGA and Devkit Coming in Q3 2020

Microsemi unveiled PolarFire FPGA + RISC-V SoC about one year ago, but at the time, development was done on a $3,000 platform with SiFive U54 powered HiFive Unleashed board combined with an FPGA add-on board from Microsemi. I’ve now been informed that Microchip has announced its Linux-capable PolarFire FPGA+RISC-V SoC would start shipping in Q3 2020 at the RISC-V summit and that a development kit will be sold for a few hundred dollars. PolarFire SoC FPGA PolarFire SoC FPGA key features and specifications: Mid-Range FPGA optimized for Low Power High-speed serial connectivity with built-in multi-gigabit/multi-protocol transceivers from 250 Mbps to 12.7 Gbps Up to 461k logic elements consisting of a 4-input Look-Up Table (LUT) with a fracture-able D-type flip-flop Up to 31.6 Mb of RAM Power optimized transceivers Up to 1420 18 × 18 multiply-accumulate blocks with hardened pre-adders Integrated dual PCIe for up to ×4 Gen 2 Endpoint […]

December 4, 2019 by Jean-Luc Aufranc (CNXSoft) - 3 Comments

Think Silicon NEOX|V is the First RISC-V ISA based GPU

We are seeing more and more RISC-V microcontrollers and processors hitting the market, but so far they all lacked a GPU for 3D graphics acceleration. Think Silicon, the make of NEMA GPU for IoT and wearables, has now announced it will demonstrate NEOX|V GPU, the first RISC-V ISA based 3D, at the RISC-V Summit at the San Jose Convention Center, on December 10-12, in San Jose, California. NEOX|V key features: Parallel multi-core and multi-threaded architecture based on the RISC-V64GC ISA instruction set with adaptive NoC (Networks-on-Chip) Configurable from 4 to 64 cores Variety of cache sizes and thread counts organized in 1 to 16 cluster elements Variety of cluster/core configurations with compute power ranging from 12.8 to 409.6 GFLOPS at 800 MHz Support for FP16, FP32, and FP64 plus SIMD instructions Beside 3D graphics, the RISC-V GPU can also be used for machine learning, vision/video processing, and open GPGPU compute […]