Beyond Semi Introduces 32-bit BA20 Core with Cortex M4 Performance Efficiency, and Cortex M0+ Silicon Area

Beyond Semiconductor and CAST have jointly announced BA20 32-bit embedded processor core with PipelineZero Architecture (zero-stage execution pipeline), that rivals with ARM Cortex A4 in terms of performance per MHz, while using about the same silicon area as an ARM Cortex M0+. which could be critical for applications such as wearables, sensors, and wireless communication, that may require both a small footprint and high performance efficiency.

Beyond Semi BA20 Block Diagram

The company’s PipelineZero micro-archirtecture can execute one instruction per cycle, hence saving energy by doing more in less time, and by operating at lower clock rates.

Key features listed for BA20 IP core:

  • PipelineZero architecture for high performance efficiency with tiny silicon footprint
    • 3.04 DMIPs/MHz (vs ARM Cortex M4: 1.25 DMIPS/MHz)
    • 3.41 Coremarks/MHz (vs ARM Cortex M4: 3.40 CoreMarks/MHz)
    • 2µW/MHz (vs ARM Cortex M0+: 3µW/MHz)
    • 10K gates (0.01mm2) in 9-track 40G (vs 0.009mm2 for ARM Cortex M0+)
  • BA2 ISA Extreme Code Density for less instruction fetching energy usage
  • Interconnect – 32-bit wide AMBA AXI4-lite bus
  • Advanced power management
    • Dynamic clock gating and power shut-off of unused units
    • Software- and hardware-controlled clock frequency
    • Wake-up on tick timer or external interrupt
  • Optional Processor Units
    • Programmable Vectored Interrupt Controller Unit
    • Memory Protection Unit
    • Timer Unit
    • Debug Unit
      • MDB support
      • Trace port support
    • ROM Patching Unit
    • IEEE-754 compliant Floating Point Unit
    • Hardware Multiplier/Divider
  • Peripherals include GPIO, UART, Real-Time Clock, Timers, I2C, and SPI
  • Memory controllers, interconnects, and more

Beyond_BA20_vs_ARM_Cortex_M BA20 Processor IP Core, and peripherals IP are available now in RTL source code (Verilog) or FPGA netlists, and BeyondStudio Eclipse-based IDE for Windows or Linux can be used for software development. The company can also provide reference design boards with JTAG and serial debug/trace for both CPU and system, but no details have been provided about these hardware platforms.

As with all Beyond Semi processor Core, BA20 is royalty-free, and only a one-time license needs to be purchased. Further details can be found on Beyond Semi BA20 PilelineZero Embedded Processor page.

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5 Replies to “Beyond Semi Introduces 32-bit BA20 Core with Cortex M4 Performance Efficiency, and Cortex M0+ Silicon Area”

  1. @renw0rp
    Not really, this is not ARM, it looks like this is a completely different design and instruction set done from scratch, more modern. They are sacrificing compatibility and established standards for performance and efficiency.

  2. @renw0rp
    I asked by email if any tradeoff were made. Here’s their answer:

    You are correct, trade-offs must be made, something must be sacrificed.

    The BA20 is not aimed at maximum performance in a given process, but at maximum efficiency (in terms of energy required for work performed). For example, BA20 will reach approx. 125 MHz in 65 LP process, though most applications will run at much lower clock frequency than that.

    Another key point is that IPC is somewhere between 0.95 – 1. It means that there are virtually no “dead” cycles – every cycle an instruction is executed. And this without branch prediction circuitry, but at expense of limiting max. frequency.

    High performance per MHz means that you can do work in less time, and power down faster and burn less battery energy. The better efficiency metric than uW/MHz are / ie. CoreMarks/uWh or CoreMarks/J or Dhrystones/uWh,…. and this was the metric that we optimized BA20 for.

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