Intel Gemini Lake Block Diagram and Yet More Info

So yesterday, I wrote about some of the new features of Intel Gemini Lake processors like native HDMI 2.0, 4-wide pipeline, 10-bit VP9, and possible built-in 802.11ac wireless controller. I went to bed, and somehow this morning I woke up with something that looks like Gemini Lake (GLK) block diagram, and a few more details.

So we indeed have HDMI 2.0 output, as well as DP 1.2a and eDP 1.4, and an embedded wireless controller via the CNVi (Connectivity Integration Architecture) block for WiFi’s MAC and Bluetooth’s MAC + Baseband modem. We’ll have plenty of USB 3.0 host interfaces, and the usual PCIe and SATA 3 interfaces. Still no UFS support, but eMMC 5.1 is supported, as well as x128 DDR4, LPDDR3 and LPDDR4 memory up to 2400 MHz (No ECC support). Cache size is confirmed to be 4MB for up to four GoldMont Plus (GLM+) cores, which combined with the wider pipeline (4 vs 3) will contribute to 10% to 15% better CPU performance compared to Apollo Lake. The Gen9LP GPU in GLK processors will come with up to 18 execution unit.

Another difference will be the update of GMM speech acceleration engine to the GNA version of the SIP with support for DNN (Dynamic Neural Networks) algorithms that could be used for applications such as Microsoft Cortana.

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6 Replies to “Intel Gemini Lake Block Diagram and Yet More Info”

  1. What is their problem?!
    Why aren’t they adding support for UFS?!
    Why does ARM SoCs support this for several years already, but Intel doesn’t?!

    This is an example that shows why Intel failed in the smartphone market! They can’t compete with ARM!!!
    Such a shame…

  2. Lack of UFS support isn’t really that much of a disadvantage as far as I am concerned.

    The other features far outweigh it.

    This will make a dent in the ARM market as long as the price differential is not too great and unlike the continued mess that Android is out of the box on ARM, it will strengthen the Windows MiniPC/Video player combination market with it’s greater consistency from opening the box.

    I think that even Gemini lake is a short stop gap though as when we get to 10nm SOC’s then ARM will have to really look over it’s shoulder because that is when I think that we will see Intel making great strides in more areas and especially back into the smartphone arena.

  3. Gen9 “LP” mean HD 6xx series, but is there one with 18 execution units, or it’s introduced with Gemini Lake, aka HD 605 for example?

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