BOOM Open Source RISC-V Core Runs on Amazon EC2 F1 Instances

The Berkeley Out-of-Order Machine (BOOM) is an open source RV64G RISC-V core written in the Chisel hardware construction language, and mainly ASIC optimized. However, it is also usable on FPGAs, and developers support the FireSim flow to run BOOM at over 90 MHz on Xilinx Ultrascale+ FPGAs found in Amazon EC2 F1 instances.

The BOOM core was created at the University of California, Berkeley in the Berkeley Architecture Research group, in order to create a high performance, synthesizable, and parameterizable core for architecture research.

BOOM RISC-V Core Block DiagramKey features of BOOM core:

  • ISA – RISC-V (RV64G)
  • Synthesizable
  • FPGA support
  • Parameterized
  • Floating Point (IEEE 754-2008)
  • Atomic Memory Op Support
  • Caches & Virtual Memory
  • Boots Linux
  • Privileged Arch v1.11
  • External Debug

BOOM is said to be inspired by the MIPS R10k and the Alpha 21264 out–of–order processors, based on a unified physical register file design (aka as “explicit register renaming”). The source code for the core can be found on Github, and documentation here, which also details how to get started.

More details may also be found on website.

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7 Replies to “BOOM Open Source RISC-V Core Runs on Amazon EC2 F1 Instances”

    1. Nah … f1.2xlarge is only about $0.50/hour as a spot instance, so about $360/month. Or $120/month if you only want to use it during office hours.

      The alternative to get similar performance on a multi-core design with cache and FPU and MMU and so forth is usually something like the $3500 VC707 FPGA board.

  1. Usuable on FPGAs usually means it’s not optimal on them (i.e. you won’t see as high a performance (subpar) on them).

    Having said this, BOOM’s been eagerly awaited to be more than an “experiment” for a bit now. It’s got real potential regardless of how you slice that.

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