AndesCore N22 RISC-V Core Supports RV32IMAC or RV32EMAC Instruction Sets

We covered Gigadevice GD32V general-purpose microcontroller with a RISC-V “Bumblebee” core last week, and I was informed that Andes Technology had recently introduced AndesCore N22 RISC-V “Bumblebee” IP core capable of supporting either RV32IMAC or RV32EMAC instruction sets.

A web search did not reveal any specific information about what “Bumblebee” RISC-V cores are exactly, or maybe it’s in reference that many can be coupled in parallel. But that’s just a small detail, let’s check out in some details what AndesCore N22 core has to offer. The RISC-V core is designed for entry-level MCUs found in IoT devices and wearables, and is capable of deeply embedded protocol processing for I/O control, storage, networking, AI and AR/VR.

AndesCore N22 RISC-V CoreHighlights of AndesCore N22:

  • AndeStar V5 (RV32IMAC) / V5e (RV32EMAC) Instruction Set Architecture (ISA), compliant to RISC-V technology plus Andes extensions architectured for performance and functionality enhancements
  • 32-bit, 2-stage pipeline CPU architecture
  • 16/32-bit mixable instruction format for compacting code density
  • Branch prediction to speed up control code
  • Configurable Multiplier
  • Physical Memory Protection (PMP)
  • Core-Local Interrupt Controller (CLIC) with selective vectoring and priority preemption
  • Flexibly configurable Platform-Level Interrupt Controller (PLIC) for supporting SoC with multiple processors
  • Advanced CoDense technology to reduce program code size
  • StackSafe hardware to help measuring stack size, and detecting runtime overflow/underflow
  • PowerBrake to digitally adjust power (via stalling pipeline)
  • Several configurations to tradeoff between core size and performance requirements
RISC-V PowerBrake
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A recent presentation in English gives us more details, and for instance, the claim is made that AndesCore N22 has “excellent PPA (Power, Performance, and Area)”:

  • Min. useful configuration: < 15K gates
  • Dynamic power: 1.36 uW/MHz @ 28nm
  • Performance: 3.95 CoreMark/MHz
  • Max. frequency: up to 700 MHz @ worst case

The document also shows the performance, footprint (code size), and efficiency of Andes N22 RISC-V core against Arm Cortex-M3 and M0+ cores in a similar configuration.

Andes N22 RISC-V vs Arm Cortex M3 / M0+
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Andes is also providing development tools including the free to download AndeSight Eclipse-based IDE, AndeSoft Software Stack, as well as two AndeShape FPGA based development boards, namely the Arduino compatible Corvette-F1  board and the full-featured ADP-XC7K development kit, and debugging hardware such as AICE-MINI+ and AICE-MICRO.

Andes N22 Software Development Environment
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AndesCore N22 core is officially supported by GNU and LLVM communities, several optimized libraries such as MCUlib and newlib, and samples programs are available.  The new RISC-V MCU core supports the open-source FreeRTOS, and the commercially supported Express Logic ThreadX real-time operating systems. The company also mentions “RISC-V Ready” operating systems such as Zephyr, RT-Thread, μC/OS-II, MyNewt, SylixOS, LiteOS, or AliOS Things, which as I understand it may not be officially supported (yet), but already work with generic RISC-V cores.

You may find more details on the product page, and if your mandarin is up to speed, you may want to watch the video below accompanying the aforelinked presentation.

Thanks to Blu for the tip

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