Marvell OCTEON TX2 CN9130, CN9131 and CN9132 SoCs Target 5G Base Stations, Edge Networking, Storage Applications

A while ago, I was informed three new Marvell processors had made it to mainline Linux, namely CN9130, CN9131, and CN9132, but at the time, the description was a bit cryptic:

The CN9130 is made of one AP807 and one internal CP115. There are three development boards that are made of this SoC:
* CN9130-DB
* CN9131-DB (with one additional modular CP115 compared to CN9130-DB)
* CN9132-DB (with two additional modular CP115 compared to CN9130-DB)

No other public information was available either, but Marvell has now published more details and those are OCTEON TX2 Infrastructure processors with four Cortex-A72 cores @ 2.2 GHz, up to 18x SERDES IO, and 10GbE.

Octeon TX2 CN9130 Block Diagram
Click to Enlarge

Octeon TX2 CN9130 key features and specifications:

  • CPU – Quad-core Armv8 Cortex-A72 @ up to 2200 MHz with 48 KB I-cache, 32 KB D-cache, 1 MB total L2 cache divided into two clusters of 512 KB ECC shared cache, 1MB L3 Cache with ECC
  • Memory I/F – 64-bits DDR4 + ECC at 1200Mhz clock
  • PCIe 3.0 – 1x Port x4 + 2x Ports x 1; total of 3 controllers and up to 6 lanes
  • Ethernet Ports – 1x 10/5 GbE port + 2x 1/2.5 GbE Ports or 2x 5 GbE Port +
    1x 1/2.5 GbE Port
  • USB 3.0 – 2 x USB 3.0 (Host/Device)
  • SATA 3.0 – 2 x SATA 3.0
  • SERDES Lanes – 6 Lanes
  • Network Subsystem
    • Configurable packet processor
    • I/O Virtualization Flexible parsing and classification
    • IPv4 and IPv6 N-Tuple classification
    • QoS, Buffer Management
    • Energy-efficient Ethernet
  • Virtualization
    • Armv8-A virtualization
    • IO virtualization, sing SMMUv2 with stage 1 and stage 2 translations
    • Virtualized DMA engines
    • Virtualized Security engine
    • Virtualized packet processor
    • PCIe with SR-IOV support
  • Package – HFCBGA 24×24 mm, 0.8 mm pitch

Octeon TX2 CN9131 CN9132

CN9131 and CN9132 add respectively one and two 88F8215 bridge chips that doubles and triples I/O’s (PCIe, Ethernet, USB, SATA and SERDES) compared to CN9130 processor. The CN913x dies are all integrated into a single multi-chip module (MCM) package comprised of an application processor (AP) and one or more Southbridge (SB).

The processor are expected to be found in 5G base stations, network and security appliances such as firewalls or routers & gateways, as well as IoT/edge servers, enterprise/SDN switches, and various networked storage solutions.

More details can be found on the product page, as well as a recent press release also covering Octeon Fusion CNF95xx SoCs built around Octeon TX2 processors and designed for “4G and 5G layer 1 baseband processing”, as opposed to “Layer 2 and 3 transport and control plane processing” for the processors covered in this article.

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4 Replies to “Marvell OCTEON TX2 CN9130, CN9131 and CN9132 SoCs Target 5G Base Stations, Edge Networking, Storage Applications”

  1. I read yesterday Marvell and Samsung are extending their collaboration to encompass infrastructure across additional segments of the radio access network. The companies have collaborated on baseband and transport processing solutions for base stations based on Marvell’s Octeon and Octeon Fusion processors. Have not a clue if the SoC in the cnx software article are used.

  2. For me these essentially look like rebranded and slightly improved Armada8040. The higher frequency may justify the switch from AP806 to AP807, but overall it’s the same. We’ve never seen the 8080 that was supposed to come with 8 cores, I suspect they were busy with the Cavium acquisition. But it’s clear that they seem to be killing the Armada product line in favor of the Octeon one, even if they mostly take the Armada technology and the Octeon brand. Probably that the latter is more known in the enterprise market and that it makes sense to use this name now for all products.

    At least I hope they progressively come back to creating new stuff because they’ve been re-heating old meals for quite a few years now, and seeing that their new devices use the same cores configuration as the latest $35 RPi is not good for their image at all! And in this segment they now have NXP’s LX2160A in front of them with 4 times the number of cores and 8 times the amount of cache, it’s about time to do something!

      1. Good catch. So they kept the Armada line for the entry level and used the Octeon Tx for the high-end, and are selling all of them under the same name. Some may experience some surprises however, because while the Armada series works out of the box in mainline kernel, I don’t think it’s even yet the case for the octeons. I also seem to remember that the octeons (called armv8.2 here) do not support 32-bit nor thumb, which means that developing on the entry level hoping to switch for production will not necessarily be helpful considering that you can discover jokes related to stuff that works on the small devices and not the big ones. And using the same name “octeon-tx2” for two totally different products is going to cause some confusion in compilers as well, which will have to decide once for all for which one they want to optimize (guess they’ll do for the large ones since the others will be a72) but again this will definitely add some confusion and integration issues.

        Probably too much marketing to try to present a nice story after having been silent for too long.

        Hopefully they’ll issue a TX3 in two years which completely fuses the two technologies and unifies the whole line in order not to reproduce the mistakes of the past where distros were scratching their heads figuring how to support the omnipresent marvell chips and regular CPUs with the same toolchain :-/

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