PicoRio Linux RISC-V SBC is an Open Source Alternative to Raspberry Pi Board

There’s a lot of interest/hype around RISC-V, and low-cost boards such as Longan Nano or Maixduino are already available, but those are based on microcontroller-class chips, even though it’s possible to run Linux on Kendryte K210 RISC-V board, it comes without MMU, so it’s not for everyone.

Linux capable RISC-V boards do exist but cost several hundred dollars or more with the likes of HiFive Unleashed and PolarFire SoC Icicle development kit. If only there was a RISC-V board similar to the Raspberry Pi board and with a similar price point… The good news is that the RISC-V International Open Source (RIOS) Laboratory is collaborating with Imagination technologies to bring PicoRio RISC-V SBC to market at a price point similar to Raspberry Pi.

PicoRio Linux RISC-V SBC

The PicoRio board was presented at the RISC-V Global Forum on September 3rd. I could not find the full presentation slides yet, but there are some screenshots here and there on Twitter giving us a few more details.

PicoRIo preliminary specifications:

  • PicoRio SoC
    • Quad-core 64-bit RISC-V (RV64GC) processor at 500+ MHz
    • 1x 32-bit RISC-V (RV32IMC) always-on core
    • Imagination Technologies PicoRio GPU (only in second revision of chip)
    • 512KB L2 cache
    • Package – 4.3 x 3.4 mm die size , fcCSP package
    • 28 nm Process
  • System memory – 16-bit LPDDR4
  • Storage – TBD, likely MicroSD card
  • Video Output – TBD
  • USB – USB 3.0 interfaces
  • I/Os – UART, I2C, SPI, etc…

PicoRio RISC-V SBC Raspberry Pi AlternativeThe first board without GPU is planned for Q4 2020, following with one with PowerVR GPU in 2021.

PicoRio aims to be open-source hardware as much as possible, with the CPU part being fully open, but the memory PHY, USB 3.0 PHY, GPU, and other I/Os will still be closed source, even though the goal is to eventually have as much IP released under a BSD-like open source license.

The board will target the Raspberry Pi price, but be more efficient with battery-powered devices in mind. PicoRio will run Linux, and support higher-level languages like WebAssembly and JavaScript.

More details should eventually surface on RIOSLab website that is currently very much work-in-progress…

Thanks to Arnaud for the tip.

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17 Replies to “PicoRio Linux RISC-V SBC is an Open Source Alternative to Raspberry Pi Board”

  1. I was compelled to comment after laughing hysterically at seeing “open source” and “Imagination Technologies” mentioned in the same breath.

    1. Last people heard from them on open source was “we’d rather die than open source anything” … oh well …

  2. This board may target the price of an Rpi board, but it’s not going to be able to perform remotely like one. It may have lower power useage, but that’ll be at the expense of 4x the CPU performance (that’s being generous to the PicoRio), more than half of the memory bandwidth.

    It’s pretty clear that their comments about being open source are vapor. The only parts that are open source are the CPU. Well, having the source for the CPU is nice and all, but it doesn’t make it any easier to support. ARM CPUs are ‘closed designs’ in the sense that they don’t share how to make your own, but how to use the CPU and how to support its features is completely open. And that’s the part that matters to 99%+ of us.

    We really need to tell the RISCV people to learn the importance and value of Open Source and to stop yelling it all the time like it’s some magic tailsman. If your open source project performs horribly compared to the closed source alternatives, then I guess I can see why that’s what you keep harping on. How about making it perform well so that it can be something other than a toy?

    1. RISC-V + Open IP blocks making up the SoC would be something but I doubt they’ll actually deliver on opening as much of it as possible.

      Given all of the “open” spin they’ve covered this in I’d expect to see the SoC design on github with instructions of how to load it into some $10K FPGA eval board. Almost no one could actually use it but it would be actually open and make the hard version of the SoC interesting.

      1. Looking at the die shot, this is clearly a soft core–which explains the horrible performance (500MHz at 22nm????). I’m not sure what value even having that open would be–aside from the 10K FPGA owners you mention.

        They make it clear from the slide that the only open parts are the CPU core. If ‘Open Source” processors are to become a thing, we need open DRAM controllers, ethernet, etc.

        1. looks like a low-power ASIC. Don’t be confused, the 22nmscale is only one of the number of factors, that determines fmax. Another extrem example: We have seen a heavily pipelined alu in 90 nm with fmax above 5 GHz (custom cells, not ASIC-Standard Cells)

          1. To be that slow at 22nm, they would have to be using sub threshold logic or something crazy agressive to save power. They would then have to remove their brain and add the USB3 PHY which probably uses 1 Watt all by itself at idle.

            Much more likely is that they just let the computer route their soft cores and it did a predictably bad job of it.

          1. If it’s a soft core synthesized for an ASIC, it’s still a soft core. If you go through and hand lay it out, you make a hard core.

  3. RISC V is interesting. Lots of things are open but lots of the money is from corporations that want to own things. Almost everything that is open has a permisive BSD-like license, not GPL-like. So stuff can be taken private.

    The architectures are open.

    Lots of software is open.

    Most useful implementations are not open. The open implementations are meant to be poured into an FPGA and thus are just not going to be fast.

    So: for individuals, the advantages or RISC V are limited at this time. This may change with several companies competing with similar offerings. But we kind of have that with ARM (albeit with only one shop designing almost all the cores).

    The Western Digial RISC-V story is kind of interesting. But no MMU or GPU.

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