Cologne GateMate A1 FPGA chip with 20,480 LE is programmable with an open-source toolchain

Cologne Chip GateMate A1 is an FPGA with 20,480 logic elements best suited for lower-power applications and programmable with an open-source toolchain based on nMigen, Yosys, and other open-source tools.

The A1 FPGA also comes with 1,280 Kbit block SRAM, four PLLs, a quad SPI interface up to 100 MHz, a 5Gbps SerDes interface, and the company offers an evaluation board to get started with development.

GateMate A1 FPGA

GateMate A1 specifications:

  • CPE Architecture
    • 20,480 programmable elements (CPE) for combinatorial and sequential logic
    • 40,960 Latches / Flip-Flops within programmable elements
    • CPE consists of LUT-tree with 8 inputs
    • Each CPE is configurable as a 2-bit full-adder or 2×2-bit multipliers
  • Features
    • 4x programmable PLLs
    • quad SPI interface up to 100 MHz
    • 1,280 Kbit dual-ported block RAM with variable data widths in 32 x 40 Kbit RAM cells
    • Multipliers with arbitrary size implementable in CPE array
    • Multiple clocking schemas
    • All 162 GPIOs are configurable as single-ended or LVDS differential pairs
    • Double data rate (DDR) support in all GPIO cells
    • 5 Gb/s SerDes
  • Power modes – low power (0.9V) , economy (1.0V), speed (1.1V)
  • Power Supply
    • No excessive start-up currents
    • Only two supply voltages needed and can be applied in any order
  • Package – 324-ball BGA package (15×15 mm)
  • Process – Globalfoundries 28 nm SLP (Super Low Power) process

Cologne FPGA family A1 to A25

As we can see in the table above, the company is also working on higher-end FPGA based on the same architecture but with up to 512,000 logic elements, up to 37,768,000 bits of block RAM, and up to 100 PLLs.

Cologne FPGAs are programmable with the Yosys framework coupled with a proprietary, but free-of-charge, place & route tool. You’ll need to register on the company’s website to have access to the pre-built binaries for Linux or Windows. Somehow the registration form does not work for me as I’m not receiving the verification email… And the documentation also gives direct access to the pre-build toolchains for Linux and Windows, plus instructions to build the tools from source.

Cologne open-source FPGA toolchain & design flow
Cologne FPGA design flow

The company also provides the GateMate A1 FPGA evaluation board with the following specifications:

  • FPGA – GateMate A1 FPGA described above
  • Memory & storage
    • 64 Mbit HyperRAM @ 166 MHz
    • 64 Mbit Quad-I/O SPI flash @ 80 MHz
    • Unpopulated footprint for secondary HyperRAM or HyerFlash module
  • Interfaces
    • USB-JTAG + USB-SPI configuration interface
    • 2 Pmod-compatible ports
    • SerDes interface via SMA
    • 6x GPIO banks
  • Power
    • Powered from USB
    • Adjustable Vcore (0.9-1.1V)
  • Dimensions – 160×100 mm (Eurocard standard)

GateMate A1 FPGA development boardThe new FPGA may be especially interesting to European users as Cologne Chip is a German company so they can be shielded from import taxes and potential trade restrictions. They also happen to be sponsored by the German government, more exactly the Federal Ministry of Economic Affairs and Energy.

The GateMate A1 FPGA evaluation board can be purchased on Elpro for about 259 Euros or Digikey for an undisclosed price since they don’t like my IP address and I’m lazy using a VPN just to check the price. But if you can wait, Olimex has published a tweet saying they had started working on a Cologne GameMate A1 board and it should offer performance similar to the AMD Xilinx Spartan 7. More details, including the documentation to get started, can be found on the product pages for the chip and evaluation board.

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