Altera has introduced the Agilex 27 FPGA and SoC family designed for AI infrastructure, high-speed networking, 6G and satellite communications, and aerospace and defense applications. The family includes 14 device models, each available as either an FPGA-only device or an FPGA SoC with integrated Arm processors
The new devices rely on Altera’s third-generation HyperFlex architecture, which the company claims delivers 1.8 times the performance per Watt compared to the previous-generation Agilex 7 FPGAs. Other features include up to 17.6 million logic elements, second-generation AI Tensor DSP blocks, an Arm Cortex-A720/A520 processor subsystem in the SoC FPGA variants, 256 Gbps transceivers, PCIe 7.0, 1.6TbE Ethernet, and LPDDR6 memory support.
Altera Agilex 27 FPGA and SoC family specifications:
- FPGA architecture – 3rd-generation HyperFlex architecture with enhanced adaptive logic modules (ALMs)
- 866K to 17.6 million logic elements (LEs)
- 274,190 to 5,683,872 ALMs
- Up to 1.8× better performance per watt compared to the previous-generation Agilex 7
- Processor (SoC variants only) – Armv9.2 Hard Processor System (HPS)
- Dual Arm Cortex-A720 cores and dual Cortex-A520 cores, with CPU speeds up to 2.3 GHz
- 2MB shared L3 cache and 512KB on-chip RAM with ECC
- AI and DSP acceleration
- 1,096 to 21,048 second-generation AI Tensor DSP blocks
- Up to 1,211 TOPS INT8 performance
- Supports INT8/9/16/32, BFLOAT16, FP16/32, TF32, and complex arithmetic
- Fixed-point, floating-point, tensor, and vector processing modes
- Memory
- FPGA
- 40Mb to 822Mb M20K memory
- 63Mb to 1,096Mb M80K memory
- 8Mb to 158Mb MLAB distributed memory
- External memory – DDR5, LPDDR4, LPDDR5/5X, LPDDR6
- 3 to 18 hard memory controllers with inline memory encryption (IME)
- Up to 9.84 Tbps external memory bandwidth
- Memory-in-package options on M-Series devices
- FPGA
- Storage – SD/eMMC interfaces
- Display – MIPI D-PHY-based display connectivity; LVDS support
- Camera – MIPI C-PHY 2.1 and D-PHY 3.0, up to 4.5 Gbps per lane, for high-speed camera and image sensor connectivity
- Networking
- Up to 10x 800GbE or 4x 1.6TbE with hardened MAC, PCS, and FEC
- Hardware MACsec support
- 3x TSN Ethernet MACs on SoC variants
- Expansion
- PCIe 6.0 x8 (up to 2 instances on selected devices)
- PCIe 7.0 x8 / PCIe 6.0 x16 (up to 6 instances on selected devices)
- Root Port (RP), Endpoint (EP), bifurcation, and Integrity and Data Encryption (IDE) support
- High-speed and medium-speed I/O banks with GPIO
- High-speed transceivers
- Up to 32x GT SerDes transceivers @ 256 Gbps
- Up to 176x GX SerDes transceivers @ 128 Gbps
- GS SerDes transceivers @ up to 32 Gbps
- NRZ and PAM4 signaling
- UCIe interface for chiplet connectivity
- USB – USB 3.1 Gen 2 (10 Gbps), USB 2.0 OTG
- Serial – I2C, I3C, SPI, OSPI, UART
- Misc – DMA controllers, timers, watchdogs, and GPIO
- Security
- Secure Device Manager (SDM) with hardware root of trust, secure boot, and device attestation
- Post-quantum cryptography (PQC) support aligned with CNSA 2.0
- Protected key storage and physical anti-tamper protection
- AES/SM4 encryption, MACsec, PCIe IDE, and inline memory encryption
- FIPS 140-3 Level 2 certifiable options
- Package – BGA packages from 27 × 27 mm to 65 × 65 mm
The Agilex 27 family features a new HyperFlow data network that connects the FPGA fabric, memory controllers, Arm processors, PCIe, and other interfaces. It uses dedicated data paths and DMA engines to transfer data without using FPGA logic resources, reducing routing congestion and leaving more resources available for AI, signal processing, and other tasks. The devices also feature third-generation HyperFlex architecture for better performance and logic utilization, along with second-generation AI Tensor DSP blocks for integer, floating-point, vector, and tensor operations used in AI and signal processing.
For robotics and physical AI applications, the FPGAs can handle sensor synchronization, image and signal preprocessing, and data transfer to external CPUs or GPUs. This allows time-critical control and safety operations to run separately from AI processing workloads. Altera also offers Agilex 27 M-Series devices with in-package memory and Direct RF-Series devices with integrated data converters through UCIe chiplets, although detailed specifications for these variants are not yet available.
Altera’s Quartus Prime Pro Edition FPGA development software supports the Agilex 27 family. The latest version 26.3 also adds QuartusIQ, an AI assistant that helps with FPGA design, debugging, finding documentation, and suggesting improvements based on the current project. It can be used directly from the Quartus GUI and can also connect to external AI tools through the Model Context Protocol (MCP).
Previously, we wrote about Intel’s Agilex SoC FPGA family with quad-core Cortex-A53 processors and up to 112 Gbps transceivers, as well as the more recent Altera Agilex 9 Direct RF-Series AGRW039 SoC FPGA with integrated 64 Gsps RF converters. The new Agilex 27 family increases logic capacity and transceiver speeds while adding Arm Cortex-A720/A520 processing, newer memory interfaces, and PCIe 7.0 support.
The company says Quartus Prime design support for Agilex 27 will be available to early-access customers in mid-November 2026, with engineering samples expected in the second half of 2027. QuartusIQ is already available as part of Quartus Prime Pro Edition 26.3. Pricing has not been announced. More details are available on the product page and in the official announcement.
Debashis Das is a technical content writer and embedded engineer with over five years of experience in the industry. With expertise in Embedded C, PCB Design, and SEO optimization, he effectively blends difficult technical topics with clear communication
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