mips News - Page 7 of 19 - CNX Software

May 6, 2019 by Jean-Luc Aufranc (CNXSoft) - 2 Comments

Linux 5.1 Release – Main Changes, Arm, MIPS & RISC-V Architectures

Linus Torvalds has just announced the release of Linux 5.1: So it’s a bit later in the day than I usually do this, just because I was waffling about the release. Partly because I got some small pull requests today, but mostly just because I wasn’t looking forward to the timing of this upcoming 5.2 merge window. But the last-minute pull requests really weren’t big enough to justify delaying things over, and hopefully the merge window timing won’t be all that painful either. I just happen to have the college graduation of my oldest happen right smack dab in the middle of the upcoming merge window, so I might be effectively offline for a few days there. If worst comes to worst, I’ll extend it to make it all work, but I don’t think it will be needed. Anyway, on to 5.1 itself. The past week has been pretty calm, […]

April 18, 2019 by Jean-Luc Aufranc (CNXSoft) - No Comments

MIPS Based TritonAI 64 AI IP Platform to Enable Inferencing & Training at the Edge

After announcing their first MIPS Open release a few weeks ago, Wave Computing is back in the news with the announcement of TritonAI 64, an artificial intelligence IP platform combining MIPS 64-bit + SIMD open instruction set architecture with the company’s WaveTensor subsystem for the execution of convolutional neural network (CNN) algorithms, and WaveFlow flexible, scalable fabric for more complex AI algorithms. TritonAI 64 can scale up to 8 TOPS/Watt, over 10 TOPS/mm2 using a standard 7nm process node, and eventually would allow both inference and training at the edge. The platform supports 1 to 6 cores with MIPS64r6 ISA boasting the following features: 128-bit SIMD/FPU 8/16/32/int, 32/64 FP datatype support Virtualization extensions Superscalar 9-stage pipeline w/SMT Caches (32KB-64KB), DSPRAM (0-64KB) Advanced branch predict and MMU Integrated L2 cache (0-8MB, opt ECC) Power management (F/V gating, per CPU) Interrupt control with virtualization 256b native AXI4 or ACE interface Here’s the […]

March 29, 2019 by Jean-Luc Aufranc (CNXSoft) - 6 Comments

Wave Computing Announces the First MIPS Open Source Release

In a surprise announcement last year, Wave Computing revealed their plans to open source MIPS architecture, and more specifically the new MIPS Release 6 architecture. The company has now started to deliver the goods with the release of the first MIPS Open Program components. Specific components of the first release include: MIPS ISA – The latest R6 version of the MIPS 32-and-64-bit architecture, including extensions such as virtualization, multi-threading, SIMD, DSP and microMIPS code compression MIPS Open Tools – Integrated development environment for embedded real-time operating systems and Linux-based systems for embedded products that enable developers to build, debug and deploy applications on MIPS-based hardware and software platforms; MIPS Open Field Programmable Gate Arrays (FPGAs)– A complete training program for community members that includes: Getting Started Package – Provides the MIPS FPGA system as a set of Verilog files, plus an overview and instructions on how to use the MIPS […]

March 4, 2019April 22, 2019 by Jean-Luc Aufranc (CNXSoft) - 2 Comments

Linux 5.0 Release – Main Changes, Arm, MIPS & RISC-V Architectures

Linus Torvalds has just released Linux 5.0: Ok, so the last week of the 5.0 release wasn’t entirely quiet, but it’s a lot smaller than rc8 was, and on the whole I’m happy that I delayed a week and did an rc8. It turns out that the actual patch that I talked about in the rc8 release wasn’t the worrisome bug I had thought: yes, we had an uninitialized variable, but the reason we hadn’t immediately noticed it due to a warning was that the way gcc works, the compiler had basically initialized it for us to the right value. So the same thing that caused not the lack of warning, also effectively meant that the fix was a no-op in practice. But hey, we had other bug fixes come in that actually did matter, and the uninitialized variable _could_ have been a problem with another compiler. Regardless – all […]

December 26, 2018December 28, 2018 by Jean-Luc Aufranc (CNXSoft) - 7 Comments

Linux 4.20 Release – Main Changes, Arm and MIPS Architectures

After Greg K-H handling Linux 4.19 release, Linus Torvalds is back at the helm, and released Linux 4.20 just before Christmas: Let’s face it, last week wasn’t quite as quiet as I would have hoped for, but there really doesn’t seem to be any point to delay 4.20 because everybody is already taking a break. And it’s not like there are any known issues, it’s just that the shortlog below is a bit longer than I would have wished for. Nothing screams “oh, that’s scary”, though. And as part of the “everybody is already taking a break”, I can happily report that I already have quite a few early pull requests in my inbox. I encouraged people to get it over and done with, so that people can just relax over the year-end holidays. In fact, I probably won’t start pulling for a couple of days, but otherwise let’s just […]

December 20, 2018December 20, 2018 by Jean-Luc Aufranc (CNXSoft) - 5 Comments

Onion Omega2 Pro OpenWrt Linux IoT Board Comes with 8GB Storage (Crowdfunding)

Onion Omega2 and Omega2 Plus are MediaTek MT7688 MIPS based WiFi boards for IoT applications that were launched in 2016 for as low as $5. Both boards run OpenWrt (LEDE at the time), and Omega2 Plus included more memory and storage with respectively 128MB RAM, 32MB flash and a micro SD card. But Onion team found out that many users needed more storage space, and they’ve now come up with Omega2 Pro model with the same processor, 128MB RAM, and large 8GB flash considering we’re talking about a board running OpenWrt 18.06 here. Onion Omega2 Pro specifications: Wireless Module – Onion Omega2S+ with SoC – MediaTek MT7688 MIPS processor @ 580 MHz System Memory – 128MB DDR2 RAM Connectivity – 2.4 GHz 802.11 b/g/n Wi-Fi 4 Antenna – 2 dBi directional chip antenna (on mainboard) & u.FL connector for external antenna (on-module) Storage – 8 GB eMMC flash USB – […]

December 18, 2018 by Jean-Luc Aufranc (CNXSoft) - 12 Comments

Wave Computing to Open Source MIPS Architecture

There has been a lot of talks about RISC-V open source, royalty-free instructions set architecture this year, including the launch of RISC-V MCUs and Linux capable RISC-V processors, and corresponding development boards such as Hifive Unleashed. This even lead Arm to create a – now shutdown – microsite telling why people should stick with Arm instead of RISC-V. While RISC-V was clearly on the rise this year, MIPS architecture once a dominant players in routers and set-top box has been on the decline, even prompting Blu to write a guest review entitled “Baikal T1 MIPS Processor – The Last of the Mohicans?” hinting at the near extincsion of MIPS based solutions. But there may be hope, or at least a last ditch effort, with Wave Computing purchasing MIPS from Imagination Technology earlier this year, and now announcing the MIPS Open Initiative to effectively open source 32-bit and 64-bit MIPS ISA […]

October 23, 2018 by Jean-Luc Aufranc (CNXSoft) - 5 Comments

Linux 4.19 Release – Main Changes, Arm and MIPS Architectures

With Linus Torvalds taking a leave from the Linux kernel project, Greg Kroah-Hartman was the one to release Linux 4.19 last Sunday: Hi everyone! It’s been a long strange journey for this kernel release… While it was not the largest kernel release every by number of commits, it was larger than the last 3 releases, which is a non-trivial thing to do. After the original -rc1 bumps, things settled down on the code side and it looks like stuff came nicely together to make a solid kernel for everyone to use for a while. And given that this is going to be one of the “Long Term” kernels I end up maintaining for a few years, that’s good news for everyone. A small trickle of good bugfixes came in this week, showing that waiting an extra week was a wise choice. However odds are that linux-next is just bursting so […]