Intel started sampling (Altera) Stratix 10 ARM + FPGA SoC in late 2016, and now the company has announced the availability the new Stratix 10 MX FPGA family wih High Bandwidth Memory DRAM (HBM2). The latter allow Stratix 10 MX FPGAs to offer up to 10 times the memory bandwidth when compared with standalone DDR memory solutions.
Intel / Altera Stratix 10 MX SoC key features and specifications:
- Processor – Quad-core ARM Cortex-A53 MP Core up to 1.5 GHz
- Logic Density Range – 1.092M LE to 2.073M LE
- Embedded Memory
- 3.5 to 8GB HBM2 high-bandwidth DRAM memory
- 45 Mbit to 90 Mbit eSRAM memory
- 86 Mbit to 134 Mbit M20K memory
- 6 Mbit to 11 Mbit MLAB memory
- Up to 7,920 18 x 19 Multipliers
- Up to 72 Transceivers up to 30 Gbps data rate (Chip to Chip)
- Hard Protocol IP – 3 EMACs, PCI Express Gen3 X 8, 10/40G BaseKR- forward error correction (FEC), Interlaken physical coding sublayer (PCS)
- Security – Secure device manager, Advanced Encryption Standard (AES) AES-256/SHA-256 bitsream encryption/authentication, PUF, ECDSA 256/384 boot code
authentication, side channel attack protection
Apache Kafka and Apache Spark Streaming are example of HPC applications that benefit from the higher bandwidth. Intel claims Stratix 10 MX can provide up to 512 GB/s with the integrated HBM2. As shown on the diagram above, HBM2 should also consume less power than DDR4 or DDR3 external memory. More details can be found on Altera Intel Stratix 10 MX FPGA product page.