At the end of last month, there was a lot of buzz about Bouffalo BL602, one of the first RISC-V SoC with built-in wireless connectivity, namely WiFi 4 and Bluetooth 5.0 LE.
We should expect more and more of those types of solutions, and Telink & Andes jointly introduced TLSR9-series of wireless audio chips for hearables, wearables, and other high-performance IoT applications. The chips are powered by an Andes D25F RISC-V 5-stage core that happens to be the first core to integrate RISC-V DSP/SIMD P-extension and offer Bluetooth 5.2, Zigbee 3.0, HomeKit, 6LoWPAN, Thread, and/or 2.4 GHz proprietary protocol.
The press release focuses on the Andes core, but an article in Chinese allows use to find more about Telink TLSR9 family’s key features:
- CPU – Andes D25F 32-bit RISC-V 5-stage core @ up to 96 MHz (2.59 DMIPS/MHz and 3.54 CoreMark/MHz) with RISC-V DSP/SIMD P-extension
- Optional NNU – AI engine supporting DNN, LSTM, and RNN neural networks
- Memory/Storage – 256KB SRAM and 1 MB to 2MB Flash
- Bluetooth 5.2 BR/EDR/LE with long-range, indoor positioning, BLE Mesh support
- Zigbee 3.0
- 2.4 GHz proprietary protocol
- SBC, OPUS, AAC, and LC3 audio codecs
- Echo cancellation, noise reduction. Optional active noise reduction (ANC) and multi-microphone environmental noise reduction (ENC).
- Peripherals – ADC, PWM, USB, I2C, SPI, UART, GPIOs…
- Security – AES, elliptic curve ECC, true random number generator; secure boot mechanism on higher-end models
- Debugging – 2-wire SWD or 5-wire JTAG debugging interface
- Power Management – Various low-power modes
- Packages – QFN, BGA
There’s also a TSLR9 development board as shown above with two DMICs, two analog microphones, four 3.5mm jacks for audio inputs and outputs, an antenna connector, mini USB, and various headers for I/Os and JTAG debugging.
Software development is done through IAR Embedded Workbench for RISC-V (EWRISC-V) tools, or a free Eclipse-based IDE with supports for GDB and OpenOCD debug tools, GCC and LLVM toolchains, and more. RTOS are also supported including FreeRTOS.
The company claims using RISC-V P-extension (RVP) makes the compact AI/ML applications possible on the edge devices with, for instance, a 14.3x speedup reported for CIFAR-10 AI models (image classification), and 8.9x speedup of keyword spotting technology. Besides the higher performance, the P-extension can also enable significant lower power-consumption since the system could run at a lower clock speed for the same performance.
If you want to learn more about Telink TLSR9 and Andes D25F core, both were discussed during a RISC-V Day in Vietnam. The part about TLSR9/DR25F starts at the 7:29:42 mark.
I could not find any information on Telink Semiconductor website about the TLSR9 family, but the Telink Wiki has information about earlier TLSR8 chips, and one may expect it to be updated for the new chips sooner or later.