Renesas announced the R-Car H1, their new automotice SoC with 4 Cortex-A9 cores clocked at 1GHz and Imagination Technologies’ SGX-543-MP2 graphics processing unit (GPU) aimed at high-end navigation systems. It also features a Renesas SH-4A high-reliability real-time processing CPU core acting as a multimedia engine (MME) .
The R-Car H1 SoC can also powered with Renesas’ IMP-X3 core (optional), a real-time image processing unit that enables developers to implement augmented reality application such as 360-degree camera views (Thanks to up to four independent input camera channels) and sign recognition.
Here’s an excerpt of the press release:
Renesas Electronics Corporation (TSE: 6723) and its subsidiary, Renesas Mobile Corporation, today announced a new member of the R-Car series of automotive systems-on-chip (SoCs), the R-Car H1, capable of delivering up to 11,650 Dhrystone MIPS (DMIPS), and ideal for the high-end car navigation market. The R-Car H1 SoC offers an innovative architecture where the application domain is powered by an ARM® Cortex™A-9 quad-core configuration running at 1 gigahertz (GHz), while the real-time domain is powered by a dedicated multimedia engine (MME) based on Renesas’ SH4A core. The R-Car’s architecture allows customers to implement features such as quick-boot, backup camera support, and media processing using the MME, while the application domain cores can be allocated to run advanced operating systems such as Linux, Windows® Automotive Embedded or QNX®.
You can read the complete press release on Renesas website.
Here are the R-Car H1 specifications provided by Renesas:
| Function | Specification | |
|---|---|---|
| Product number | R-Car H1 (R8A77790) | |
| Power supply voltage | 3.3 V (IO), 1.5 V (DDR3), 1.2 V (Core), 2.5 V (PCIe, MLB), 1.8 V (SDIF UHS-I) | |
| CPU core | ARM® Cortex™-A9 Quad (with NEON™) | SH-4A core |
| Maximum operating frequency | 1000 MHz | 800 MHz |
| Processing performance | 10000 DMIPS | 1760 DMIPS, 5600 MFLOPS |
| Cache memory | Instruction cache: 32 KB Operand cache: 32 KB |
Instruction cache: 32 KB Operand cache: 32 KB |
| External memory | DDR3-SDRAM (DDR) Maximum operating frequency: 500 MHz Data bus width: 32 bits × 2 channel (4 GB/s × 2 ch) |
|
| Expansion bus | Flash ROM and SRAM, Data bus width: 8 or 16 bits |
|
| PCI Express 2.0 (1 lane) | ||
| Graphics | PowerVR SGX543MP2 (3D) | |
| Renesas graphics processor (2D) | ||
| Video | Display out × 2 ch (RGB888) | |
| Video input x 2 ch | ||
| Video decode processor (H.264/AVC, MPEG-4, VC-1) | ||
| Media RAM | ||
| JPEG acceralator | ||
| TS interface | ||
| Video image processing (color conversion, image expansion, reduction, filter processing) | ||
| Distortion compensation module (image renderer) × 4 ch | ||
| Image recognition processor | ||
| Audio | Sound processing unit × 2 ch | |
| Sampling rate converter × 10 ch | ||
| Sound serial interface × 10 ch | ||
| MOST DTCP | ||
| Storage interfaces | USB 2.0 host interface × 3 ports (w/ PHY) | |
| SD host interface × 4 ch | ||
| Multimedia card interface | ||
| Serial ATA interface | ||
| In-car network automotive peripherals | Media local bus (MLB) interface × 1 ch (6-pin / 3-pin interface selectable) | |
| CAN Interface × 2 ch | ||
| IEBus interface | ||
| GPS baseband module | ||
| Security | Crypto engine (AES, DES, Hash, RSA) | |
| Secure RAM | ||
| Other peripherals | DMA controller LBSC DMAC: 3 ch / SuperHyway-DMAC: 4 ch / HPB DMAC: 39 ch |
|
| 32-bit timer × 9 ch | ||
| PWM timer × 7ch | ||
| I2C bus interface × 4 ch | ||
| Serial communication interface (SCIF) × 8 ch | ||
| Serial peripheral interface (HSPI) × 3 ch | ||
| Ethernet controller (IEEE802.3u, RMII, without PHY) | ||
| Interrupt controller (INTC) | ||
| Clock generator (CPG) with built-in PLL | ||
| On-chip debugger interface | ||
| Low power mode | DPS/VS (CPU core, PowerVR SGX543MP2, VPU, IMP) AVS (adaptive voltage scaling) function DDR-SDRAM power supply backup mode |
|
| Package | 832-pin FCBGA (27 × 27 mm) | |
| Development environment | ICE for ARM CPU available from different vendors | |
| Evaluation board | A user system development reference platform offering the following features is also available, enabling the users to carry out efficient system development. (1) Includes car information system-oriented peripheral circuits, providing users with an actual device verification environment. (2) Can be used as a software development tool for application software, etc. (3) Allows easy implementation of custom user functions. |
|
| Middleware | Wide variety of middleware such as H.264, MPEG-4 and VC-1 for video is available to realize complete system concept. | |
Renesas R-Car H1 will be supported by several operating systems including Linux, Windows Automotive Embedded and QNX. It will also probably be supported by Montavista Genini-compliant Automotive Technology Platform as R-Car M1 (previous version of automotive SoC) is already supported.
Samples of Renesas’ R-Car H1 SoC will be available starting in November 2011. Mass production is scheduled to begin in December 2012 and Renesas expects it to reach a cumulative 100,000 units per month by December 2013.
You can find more information on Renesas R-Car H1 page.
Jean-Luc started CNX Software in 2010 as a part-time endeavor, before quitting his job as a software engineering manager, and starting to write daily news, and reviews full time later in 2011.
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