Home > Hardware, Processors, Xilinx Zynq > lowRISC Open Source SoC Project Announces its First Release with Tutorials for Simulators and Zedboard

lowRISC Open Source SoC Project Announces its First Release with Tutorials for Simulators and Zedboard

lowRISC project aims to produce a completely open-source SoC (System-on-Chip) based on the 64-bit RISC-V instruction set architecture, as well as a corresponding development board, thus eventually producing a fully open hardware systems. The project has now announced its first release “tagged memory preview release” with a tutorial explaining how this has all been designed, and how to run simulations with software tools, or FPGA boards such as Zedboard.

lowRISC_Rocket_Chip

Rocket Chip Block Diagram

 

The project is based on Rocket core, written in Chisel language by the RISC-V team at UC Berkeley. Chisel can generate code to produce a cycle-accurate C++ emulator, Verilog optimised for FPGAs or Verilog for use in an ASIC flow.If you want to try it out, you’ll need a Linux machine, preferably running Ubuntu 14.04 64-bit, with GNU GCC 4.8 installed, and follow the tutorial in order to get the source code, and build tools such as riscv64-unknown-elf-gcc compiler, and Spike simulator, as well as a RISC-V Linux kernel. Finally, they’ll show you how to run various simulations using Spike, the C++ emulator, or an FPGA board.

This is only a first step, and much more work is needed, with the organization expecting to provide more features in the next releases including “tag support in the Spike simulator and support for the L2 cache, as well as a better ISA and core support for tags”, and later on, the development of an “untethered version of the SoC with the necessary peripherals”.

  1. anon
    April 14th, 2015 at 16:26 | #1

    Did try to replace my aging OpenRISC 1200 with couple of RISC-V versions floating around, did not manage to get the data move between the L2 and ALU(s) correctly, and the execution stalls instantly after first cache line, of course those were hobby projects from people just trying out to do RISC-V -compatible core, so they were WIP.

    Need to try out this one, maybe now there is code for all necessary functions implemented.

    Of course only have Spartan-6 testbed, so not the fastest thing around, need to move to Kintex-era soon.

    Interesting to see how much more “modern” RISC-V ISA gets on the IPC versus the OpenRISC (about 1.4/MHz CoreMark).

  2. ade
    April 14th, 2015 at 17:12 | #2

    Would a low-cost spartan6 educational board such as http://www.cnx-software.com/2015/04/07/50-mimas-v2-spartan-6-fpga-development-board-comes-with-a-vga-port-64mb-ram/ be able to support it ?

  3. April 14th, 2015 at 22:02 | #3

    @ade: Not currently, but ‘untethering’ the core from a host processor is one of the next things we hope to do, and we’d like to get a baseline configuration that people can play with on low cost development boards such as the one you mention.

  4. kcg
    April 15th, 2015 at 00:57 | #4

    anon :
    Interesting to see how much more “modern” RISC-V ISA gets on the IPC versus the OpenRISC (about 1.4/MHz CoreMark).

    Any reference to this? Thanks! Karel

  1. No trackbacks yet.