Freescale Launches i.MX 7 Series Cortex A7 + Cortex M4 Processors for IoT Applications

Freescale announced plans for i.MX 7 and i.MX 8 processors in 2013, but it’s only in the last few months there have been some patchsets submitted to the ARM Linux Kernel mailing list, and so far all documentation was only available to companies and developers under NDA. Now the company has officially launched i.MX 7 series, and although all documents are not available yet, Freescale has released a factsheet providing an overview about the processors. Freescale i.MX 7 series processors targets applications such as wearables, e-readers, secure point-of-sale equipment, smart home controls, industrial automation products and other IoT solutions.

Freescale_i.mx7_Block_Diagram
Freescale i.MX 7Dual Processor Block Diagram (Click to Enalrge)

Two processors are currently available: the single core i.MX 7Solo processor, and the dual core i.MX 7Dual processor. Both basically share the same specifications, but beside the extra Cortex A7 core, i.MX 7Dual also adds on extra USB host port, a PCIe interface, an extra Gigabit Ethernet port, and a 4th generation EPD controller.

Freescale i.MX 7 specifications:

  • Main CPU
    • i.MX 7Solo – ARM Cortex A7 @ 800 MHz with 512KB L2 cache, 256KB SRAM, 96KB ROM
    • i.MX 7Dual – 2x ARM Cortex A7 @ 1.0 / 1.2 GHz with 512KB L2 cache, 256KB SRAM, 96KB ROM
  • Secondary CPU – ARM Cortex M4 @ 266 MHz
  • Memory I/F
    • 16-/32-bit DDR3/DDR3L and LPDDR2/3 @ 533 MHz
    • MMC 5.0; 3x SD 3.0
    • NOR Flash/SRAM I/F
    • 8-bit NAND I/F
    • Dual channel Quad SPI
  • Connectivity – 1 or 2 Gigabit Ethernet (AVB)
  • Display
    • 24-bit parallel RGB
    • MIPI DSI (2 lanes)
    • EPD controller (7Dual only)
  • Camera
    • Parallel CSI (up to 24-bit)
    • MIPI CSI (2 lanes)
  • Other Interfaces
    • 1 or 2 USB 2.0 host (w/ PHY), 1x USB 2.0 host interface (w/ HSIC)
    • 7x UART, 4x I2C, 4x SPI
    • 3x I2S
    • 2x CAN
    • 4x PWM
    • 2x FlexTimer
    • 2x SmartCard I/F
    • 2x 12-bit ADC
    • PCI-e slot (1x lane, 7Dual only)
  • Security with tamper resist – Secure RTC, RSA 4096, Ciphers, 10-pin tamper, etc…
  • Manufacturing – 28nm ultra low leakage process technology

Freescale claims their i.MX 7 Series processors consume about one third of their i.MX 6 Series based on Cortex A9 cores, with a core efficiency of 15.7 DMIPS/mW, and a new Low Power State Retention mode (LPSR) of 250 μW. The processors will also be coupled with the new PF3000 PMIC to achieve higher efficiency.

SABRE board for Freescale i.MX 7 processors
SABRE board for Freescale i.MX 7 processors

A SABRE board with i.MX 7Dual will also be available, and integrate a PF3000 PMIC, Wi-Fi 802.11 ac/a/b/g/n, Bluetooth 4.1 and an SD card preinstalled with a Linux based operating system, and Android is also available from Freescale. I could not find details or pricing (usually around $500) for the development board.

i.MX 7Solo and i.MX 7Dual processors are sampling now, with mass production scheduled for November 2015. More information should soon become available on Freescale i.MX 7 Series product page.

Thanks to Nanik for the tip.

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11 Comments
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Demetris
5 years ago

WTF instead of going forward with 64bit era we get to see new products with a downgrade to A7? NO! thank you

Harley
Harley
5 years ago

What no HDMI 2.0 and 4K HEVC (H.265) video decoding?

Ian Tester
5 years ago

@Demetris
i.MX8 will be 64-bit, although using the low-end Cortex-A53 cores.

William Henning
5 years ago

I like the gigabit Ethernet, and the duo has a PCIe lane that could be used for a SATA controller.

The addition of an M4, presuambly as an I/O processor, is also quite interesting.

I could see using this in industrial apps.

Al
Al
5 years ago

Any word on how the merger between NXP and Freescale is going ?

Tore
Tore
5 years ago

@Ian Tester
If I recall correctly they have recently switched from A53 to A57 cores for the i.MX8 series. That one will be very interesting. Wonder what GPU/VPU solution they’ve chosen though.

Boris Mihailov
Boris Mihailov
5 years ago

512 KB L2-cache, instead of with “512MB L2 cache” in text above.
Interested for real-time applications with HMI.

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