There are plenty of standards for systems-on-module that are supposed to allow interoperability between vendors. For example vendor 1 may create a Qseven SoM that works with vendor 2’s Qseven compliant carrier board which should accept any Qseven compatible module, although in practice, there are always some small differences that may cause problems.
Many of those standards are managed by SGET (Standardization Groups for Embedded Technologies) including SMARC (“Smart Mobility ARChitecture”), Qseven, and Embedded NUC. A recent post on ADLINK Technology alerted us of the publication of SMARC 2.1 hardware specification (PDF) with the following changes:
- Incorporated Errata 1.1 Rev. 2 (2/9/2017)
- Updated signal tables with pin number, power domain, termination information…
- Added details for eDP[0:1]_HPD
- Added SERDES as alternative function for PCIeC and PCIeD
- Added MDIO Interface
- Updated power domains and power sequencing
- Added two extra GPIOs
- PCIe Clock Request signals for PCIeA and PCIeBat at previous locations
- Changed fill order for MIPI CSI (CSI1first, then CSI0)
- Added CSI 2 and 3 on extra optional connector
- USB client mode defined more clearly
- Added sleep power domain
- Redefined JTAG connector
ADLINK explains the most important changes in SMARC 2.1 are support for up to 4 MIPI CSI ports to better serve the needs of the AI and Robotics markets, and the ability to multiplex SERDES signals over the 3rd and 4th PCIe x1 interfaces for additional Ethernet ports potentially up to four Gigabit Ethernet interfaces. The more detailed information about every pin’s power domain and PU/PD status should simplify carrier board designs and improve the level of compatibility and interoperability between module designs, architectures (x86 and ARM) and vendors.