AMD Versal Premium Gen2 SoC FPGA family features Arm Cortex-A72/R5F cores, high-end FPGA fabric, PCIe Gen6, CXL 3.1 interfaces

AMD Versal Premium Series Gen 2 SoC FPGA combines dual-core Cortex-A72 and dual-core Cortex-R5F processors with high-end FPGA fabric with up to 3.2 million logic cells and CXL 3.1 (Compute Express Link), PCIe Gen6, and DDR5/LPDDR5X high-bandwidth interfaces for data center, communication equipment, test & measurement, and aerospace & defense data-intensive applications.

AMD Versal Premium Gen 2

AMD Versal Premium Gen2 specifications:

  • CPU cores
    • Dual-core Arm Cortex-A72 application core, 48 KB/32 KB L1 Cache w/ parity & ECC; 1 MB L2 Cache w/ ECC
    • Dual-core Arm Cortex R5F, 32 KB/32 KB L1 Cache, and 256 KB TCM w/ECC
  • Memory – 256MB on-chip with ECC
  • FPGA fabric
    • System Logic Cells – Up to 3,273,480
    • LUTs – Up to 1,496,448
    • DSP Engines – Up to 7,616
  • Interfaces connected to CPU cores
    • 2x Ethernet
    • 2x UART, 2x SPI, 2x I2C
    • 2x CAN-FD
    • 1x USB 2.0
  • FPGA memory, interfaces, I/Os, and transceivers
    • Up to 327 Mbit memory @ 273 GB/s (LPDDR5X)
    • Up to 2x 100Gbps multi-rate Ethernet MAC
    • Up to 3x 600Gbps Ethernet MAC
    • Up to 6x LDPC Decoder
    • 2x PCIe Gen6x8, CXL 3.1
    • Up to 736x high-performance I/Os (XSIO)
    • Up to 56x GTM2 transceivers (up to 112Gbps)
    • 16x GTM2 transceivers (CPM6/GT Direct mode – 64Gbps/32Gbps)
  • High-speed crypto engines
    • AES-GCM-256/128 engines
    • Up to 800 Gb/s of line rate encryption throughput
    • 400Gbps of MACsec, IPsec, and bulk encryption per engine
AMD Versal Premium Gen2 block diagram
Simplified block diagram

Applications range from data centers for compute acceleration, custom networking, and computational storage to test & measurement equipment (protocol analyzers, wireless testers, network testers), communication equipment (5G & 6G wireless base stations, security appliance), and aerospace and defense (avionics, radar, and cognitive radio/SDR).

There will be four parts as shown in the table below with 2VP3102, 2VP3202, 2VP3402, and 2VP3602 mostly differing in terms of FPGA fabric and related interfaces with the Arm processing system is the same across all SKUs. AMD did not discuss too much about software support, although the company mentioned support for the AMD Vivado Design Suite and the AMD Vitis unified software development platform.

AMD Versal 2VP3102 2VP3202 2VP3402 2VP6302 SoC FPGA comparison

But there’s still plenty of time as the AMD Versal Premium Series Gen 2 development tools are only expected to be available in Q2 2025, followed by samples by early 2026. Production shipments are expected to begin in the H2 2026. Additional information may be found on the product page and press release. Note the AMD Versal Premium is not to be confused with the Versal Prime as AMD themselves did in their press release…

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4 Replies to “AMD Versal Premium Gen2 SoC FPGA family features Arm Cortex-A72/R5F cores, high-end FPGA fabric, PCIe Gen6, CXL 3.1 interfaces”

    1. yeah, funny, its a big microcontroller, that nobody asked for…?
      curious that they didnt use any riscv… I think its to not advertise a rival.

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