As SiFive has a portfolio of RISC-V cores ranging from low-power E2-series to high-performance U8-series cores with performance similar to Cortex-A7x cores, the company has not released new cores for a while, and instead focuses on improving their current RISC-V cores.
We saw that last year with the SiFive 20G1 release that improved performance & efficiency, and lowered the silicon area for the same features set. SiFive further improved its cores and ecosystem with the latest SiFive 21G1 release.
The main new features brought by SiFive 21G1 release include:
- SiFive 2-Series and 7-Series processors are now available with the “Bit Manipulation” extension, RV32B, with Zba and Zbb extensions. This can accelerate Cryptographic Hash algorithms by up to 35%
- Support for FP16 half-precision floating-point computation in order to reduce memory size and power consumption, and for some AI workloads
- The memory map is now fully programmable
- SiFive RV64 processors support up to 48-bit virtual addressing and 47-bit hardware addressing through the Sv48 option for systems with huge memory requirements
- New features for time-critical applications with the 7-series processors integrating a “Core Local Port”, an ultra low latency, high-bandwidth interface, and support for the new RISC-V NMI specification designed for mission critical applications.
- Security – The Hardware Crypto Accelerator component (SiFive Shield) now comes with a Public key accelerator (HCA-PKA).
- A new and improved C-library to achieve optimal performance while reducing code size by up to 25% compared to the previous 20G1 release.
- Debugging – The type of tracing (history or branch) is now selectable, as well as the number of communication channels and trace buffer size. The History Trace Messages (HTM) offers 5x compression capability for higher performance systems.
All the improvements in the 21G1 release increase benchmark performance to 5.18 CoreMarks/MHz and 2.63 Dhrystone/MHz for 7-series RISC-V processors.