Renesas has launched its first RISC-V processor family with the RZ/Five general-purpose microprocessors based on an Andes AX45MP 64-Bit RISC-V CPU core, and with long-term Linux support via the industrial-grade CIP Linux that offers maintenance for over 10 years.
The RISC-V processor is pin-to-pin compatible with the Arm Cortex-A55/M33–based RZ/G2UL processor family, and while being a general-purpose family, the RZ/Five chips are specifically well-suited to IoT endpoint devices such as gateways for solar inverters or home security systems.
Renesas RZ/Five key features and specifications:
- CPU – Single-core 64-bit RISC-V AX45MP core @ up to 1.0 GHz
- Internal Memory – 128KB SRAM with ECC
- Memory I/F – 16-bit DDR4-1600 or DDR3L-1333 memory interfaces with in-line ECC; up to 4GB RAM
- Storage I/F – 2x SD/eMMC interfaces, SPI flash interface
- Networking – 2x Gigabit Ethernet MAC
- USB – 2x USB 2.0
- Audio – 4-channel serial sound interface (SSI)
- Serial – 2x CAN/CAN-FD interfaces, 5-channel serial communication interface with FIFO (SCIF = UART), 2-channel serial communication interface (SCI),
- Analog – 2-channel 12-bit ADC, thermal sensor
- I/Os – 4x I2C, 3x Renesas SPI interfaces, GPIOs
- Timers – Watchdog timer, 3x 32-bit general timers, 9-channel multi-function timer pulse unit (x8 16-bit, 1x 32-bit)
- Security – 1Kbit OTP memory, secure boot, crypto engine, secure JTAG
- Supply Voltage – TBD (as per user’s manual!)
- 11 x 11 mm 266-pin BGA package (Only one Gigabit Ethernet port)
- 13 x 13 mm 361-pin BGA package pin-compatible with the RZ/G2UL family
As can be seen from the table above, RZ/Five is basically the RISC-V equivalent of RZ/G2UL Arm processor, except it lacks a sub-CPU (Arm Cortex-M33), and there’s no display/camera function at all (RZ/G2UL comes with a parallel interface for displays, and a 4-lane MIPI CSI interface for cameras).
As mentioned in the introduction, Renesas RZ/Five processors run Linux, more specifically Civil Infrastructure Platform (CIP) Linux designed for industrial application with long-term maintenance support of more than 10 years. The RZ SMARC Evaluation Board Kit will be offered with a SMARC 2.1 compliant carrier board, that will allow to easily test Renesas RISC-V (RZ/Five) and Arm (RZ/G2UL) since they share most of the same interfaces.
There’s limited information on the product page at this stage, but eventually, I’d expect plenty of documentation and resources just like for the Arm version with a Yocto Linux BSP, a user’s manual, PCB design guides, SMARC PCB design files, and much more. We’ve also been told that Andes has worked with Renesas to make an open manual for the AX45MP in order to make Linux programming easier, and it should be available in the next few days/weeks.
Renesas says samples of the RZ/Five RISC-V MPUs are available now, and mass production should start in July 2022.
Thanks to Mipl and Florian for the tip.
Jean-Luc started CNX Software in 2010 as a part-time endeavor, before quitting his job as a software engineering manager, and starting to write daily news, and reviews full time later in 2011.
4 Replies to “Renesas introduces RZ/Five Linux-capable 64-bit RISC-V microprocessor family”
Typo? “Only on Gigabit Ethernet port” maybe *one* Gigabit port?
Really nice piece of silicon. Waiting for a development board release :).
This could be an interesting chip for industrial use; the ARM versions start around $8 at Mouser (but aren’t currently stocked).
So seems riscv has left tao bao and reached the mainstream