If you need to control or debug multiple devices over UART devices, you’d be glad to learn WCH has just launched the CH348 USB to serial chip with eight UART ports.
Two models are offered CH348L in an LQFP100 package and CH348Q in an LQFP48 package. Both offer eight UART interfaces, but CH348L comes with more CTS/RTS and DTR/hardware flow control signals, as well as DTR, DCD, RI signals, and support for independent voltage for I/Os.
CH348 key features specifications:
- High-speed USB device interface
- Hardware full-duplex serial port, integrated independent transmit-receive buffer
- Baud rate varies from 1200bps to 6Mbps.
- The serial ports support 8 data bits, odd, even, and none parity, 1/2 stop bit.
- Each serial port comes with a 2048-byte receiving FIFO and a 1024-byte transmitting FIFO.
- Signals RTS, DTR, DCD, RI, DSR, and CTS supported for hardware flow control
- The MODEM interface signal pins and 485 transmit and receive control pins:
- CH348Q contains 4 groups of CTS0~3/RTS0~3, and TNOW0-3 (DTR0-3).
- CH348L contains 8 groups of CTS0-7/RTS0-7, DSR0-7, DCD0-7, RI0-7, and DTR0~7 (TNOW0-7).
- Supports half-duplex, status TNOW, used for controlling RS485 to transmit-receive switch.
- Up to 48-channel GPIO input and output.
- Supports RS232/RS485/RS422 interface, through external voltage conversion chip.
- Serial I/Os of CH348L are power supply independently via VIO pins with support for 3.3V, 2.5V, 1.8V
- Built-in EEPROM used to configure the chip of VID, PID, maximum current value, vendor and product information string, etc.
- Operating voltage – 3.3V.
- LQFN48 48-pin 7x7mm
- LQFP100 100-pin 14×14 mm
WCH says serial terminal applications under Windows can work without any modification, so I suppose the same must be true under Linux, where the USB device just enumerates eight serial ports. Developers only using the Tx/Rx signals and no hardware flow control would have up to 48x GPIO to play with, so it might be quite a versatile chip for USB to UART, RS232, RS485, and GPIO.
The good news is that WCH shared the documentation on Github, but they did so in a weird way since they are just updating a zip file with all datasheet for CH34x chips as they get released, instead of having a directory, and commit new files or revision as they come by.
Both CH348 chips are available for pre-order on LCSC with “interesting” pricing since CH348L is sold for $4.8076, while the small CH348Q goes for $9.7377. It might be a typo for $4.7377, as in quantities, CH348Q becomes cheaper as it should be.
Jean-Luc started CNX Software in 2010 as a part-time endeavor, before quitting his job as a software engineering manager, and starting to write daily news, and reviews full time later in 2011.
Sounds like a relatively cheap way to build a simple multichannel lorawan gateway… If the ports and gpio are mapped 1:1, that is.
@andelf said: “Sounds like a relatively cheap way to build a simple multichannel lorawan gateway… If the ports and gpio are mapped 1:1, that is.”
The problem with that approach is you end up with a bunch of co-located cheap LoRa modules (e.g. SX1276-based UART/868MHz or 915MHz) each with it’s own antenna interface and no efficient way to combine/divide the RF amongst them to/from a single antenna. A proper LoRaWAN gateway is much more expensive (over-priced IMO), but it doesn’t have that problem.
At my post time on LCSC: CH348L, 10 in-stock, CH348Q, 0 in-stock.
Nice IC. Someone knows if is it possible to control extra pins from python as pyserial?