ESP32-H4 low-power dual-core RISC-V SoC supports 802.15.4 and Bluetooth 5.4 LE

Espressif Systems has formally announced the ESP32-H4 low-power dual-core 32-bit RISC-V wireless microcontroller with support for 802.15.4 and Bluetooth 5.4 LE portfolio after having unveiled it at CES 2024. It’s the first Espressif chip to support Bluetooth 5.4 LE with previous models such as ESP32-H2 or ESP32-C6 only supporting Bluetooth 5.0/5.2.

Besides BLE 5.4 support, the new ESP32-H4 dual-core RISC-V WiSoC is an evolution of the ESP32-H2 single-core chip with PSRAM support (up to 4MB built-in), additional GPIOs (36 vs 24), touch sensing GPIOs, and some extra security features such as a power glitch detector also found in the recently announced ESP32-C61.

ESP32-H4 block diagram

ESP32-H4 specifications:

  • CPU – Dual-core 32-bit RISC-V core (at up to 96 MHz)
  • RAM – 320KB KB SRAM, optional PSRAM up to 4MB
  • Storage – 128KB ROM, External flash support
  • Wireless connectivity
  • Peripherals
    • Up to 35x GPIOs
    • Support for I2C, I2S, SPI, UART, LED-PWM, ADC, Timers, DMA, TWAI, USB-OTG, and MCPWM
    • Event Task Matrix for automation-triggered tasks
    • 14x touch sensing GPIOs for HMI applications
    • Low Power IOs
  • Security
    • ECC-based secure boot
    • AES-128/256-XTS-based flash encryption
    • Cryptographic accelerators
    • True Random Number Generator (TRNG)
    • Power Glitch Detector (that seems to be different from the Brownout detector in earlier Espressif chips)
  • Misc – RTC, Watchdogs
  • Power Management
    • Integrated DC-DC converter for ultra-low-power, energy-efficient operation.
    • Granular activation of peripherals in low-power modes (see block diagram above)
Espressif ESP8266 ESP32 SoC portfolio
12 ESP8266/ESP32 SoCs have been launched or announced so far

Espressif expects the ESP32-H4 Bluetooth 5.4 and 802.15.4 wireless microcontrollers to be found in wearables, healthcare devices, LE Audio devices, low-power sensors, and other complex IoT applications including battery-powered Matter over Thread devices. The dual-core RISC-V SoC will be supported by the ESP-IDF framework as well as the ESP-Matter-SDK for Matter-enabled devices.

Espressif did not provide any availability information, but if we take the ESP32-H2 announcement (August 2021) and the launch of ESP32-H2 hardware (May 2023), I’d have to say see you in 2026 for the ESP32-H4 modules and devkits! But in all fairness, ESP32-H4 hardware should come quite faster since a lot of the hard work done on the ESP32-H2 can certainly be reused on the ESP32-H4. What is coming very soon is the ESP32-P4 as Espressif Systems made some noise about it a few weeks ago, and I’ve been asked to review an ESP32-P4 module/board by a third party that will come out in June.

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12 Replies to “ESP32-H4 low-power dual-core RISC-V SoC supports 802.15.4 and Bluetooth 5.4 LE”

    1. This chip is similar to the C3, so I’d expect to be priced about the same. So a little more than the H2. All of their chips are under $2.00, some as low as $0.50.

  1. What’s the difference between the three watchdogs? A super watchdog usually seems to denote one that’s off-chip.

    1. quite useful actually; use one core to handle the radio (BLE or Zigbee) and the other to handle time sensitive real-time tasks. two low-speed cores are better than one high-speed core when it comes to scheduling complexity.

  2. I have to say, I’m starting to be very unsure about the differences between all these different ESP32 models. There are now 4 with thread and ZigBee, a whole bunch with WiFi 6, all with a couple of differences that don’t seem too massive. At this point, why pick one model over another?

    1. Choose the radio standards you need
      The type of core (Tensilica or RISC V)
      Number of cores
      Amount and type of I/O pins
      Specific peripherals like ethernet or CAN, etc.
      Also ram, rom, etc. differ…

      Basically as an Arduino replacement most any works, else you have to invest a bit of time.

    2. This is because you likely don’t care about the differentiating features. For example the S2 and S3 have an LCD controller and the others do not.

  3. The glitch detection seems to be a counter measure against reading out of protected memory.

  4. I am much more curious about the results of CNX’s June ESP32-P4 EV board test result than the ESP32-H4.

  5. So can this finally draw average current in microamps instead of (tenths of) miliamps when using BLE?

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