Posted on by Jean-Luc Aufranc (CNXSoft) - 2 Comments on Xilinx Introduces Kria K26 SoM and vision AI devkit based on Zynq Ultrascale+ XCK26 FPGA MPSoC

Xilinx Introduces Kria K26 SoM and vision AI devkit based on Zynq Ultrascale+ XCK26 FPGA MPSoC

Kria V260 Vision AI Starter Kit

Silicon vendors will usually focus on chip design, and provide an expensive evaluation kit to early customers, leaving the design of cost-optimized boards and system-on-modules to embedded systems companies. But Xilinx has decided to enter the latter market with the Kria portfolio of adaptive system-on-modules (SOMs) and production-ready small form factor embedded boards starting with Kria K26 SoM powered by Zynq UltraScale+ XCK26 FPGA MPSoC with a quad-core Arm Cortex-A53 processor, up to 250 thousand logic cells, and a H.264/265 video codec designed for Edge AI applications, as well as computer vision development kit. Kria K26 System-on-Module Kria K26 module specifications: MPSoC – Xilinx Zynq Ultrascale+ custom-built XCK26 with quad-core Arm Cortex-A53 processor  up to 1.5GHz, dual-core Arm Cortex-R5F real-time processor up to 600MHz, Mali-400 MP2 GPU up to 667MHz, 4Kp60 VPU, 26.6Mb On-Chip SRAM, 256K logic cells, 1,248 DSP slices System Memory – 4GB 64-bit DDR4 (non-ECC) Storage – 16GB eMMC flash, 512 Mbit QSPI flash 2x 240-pin board-to-board […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 2 Comments on Xilinx open sources Vitis HLS FPGA tool (Front-end only)

Xilinx open sources Vitis HLS FPGA tool (Front-end only)

Vitis HLS software architecture

While there are some open-source programs for FPGA development such as Symbiflow or Yosys, FPGA vendors usually only provide closed-source programs for developers wanting to work on their chips. But Xilinx has recently made a move to fulfill its “commitment to supporting open-source initiatives for developers and researchers” with the release of the source code of Vitis HLS Front-End. What is Vitis HLS exactly? Before we look at the source code release, we may want to know what Vitis HLS does exactly. The company describes it as a high-level synthesis (HLS) tool that allows C, C++, and OpenCL functions to become hardwired onto the device logic fabric and RAM/DSP blocks. It implements hardware kernels in the Vitis application acceleration development flow, and to use C/C++ code for developing RTL IP for FPGA designs in the company’s Vivado Design Suite. Vitis HLS design flow goes as follows: Compile, simulate, and debug the C/C++ algorithm. View reports to analyze and optimize the […]

Posted on by Ayo Ayibiowu - No Comments on MYIR launches FZ5 EdgeBoard AI Box for AI on the Edge

MYIR launches FZ5 EdgeBoard AI Box for AI on the Edge

FZ5 EdgeBoard AI Box

Back in July of this year (2020), MYRI technology announced the MYIR’s FZ3 deep learning accelerator card powered by the Xilinx Zynq UltraScale+ ZU3EG Arm FPGA MPSoC and it is capable of delivering up to 1.2TOPS computing power. With only a few months since that launch, MYRI technology is now announcing another two related sets of products – FZ5 EdgeBoard AI Box and the FZ5 Card. The FZ5 EdgeBoard AI Box is an AI-focused computing platform that is based on the FZ5 AI Accelerator card which is an upgrade of the FZ3 card. The FZ5 looks more like a single board computer than an actual computing card. The FZ5 accelerator is powered by the Xilinx Zynq UltraScale+ ZU5EV MPSoC which features a 1.5 GHz quad-core Arm Cortex-A53 64-bit application processor, a 600MHz dual-core real-time Arm Cortex-R5 processor, a Mali400 embedded GPU and is capable of delivering up to 2.4 TFLOPS as compared to the predecessor FZ3’s 1.2 TFLOPS based on the Xilinx […]

Posted on by Jean-Luc Aufranc (CNXSoft) - No Comments on Linaro Connect SF 2017 Welcome Keynote – New Members, Achievements, the Future of Open Source, and More…

Linaro Connect SF 2017 Welcome Keynote – New Members, Achievements, the Future of Open Source, and More…

Linaro Connect San Francisco 2017 is now taking place until September 29, and it all started yesterday with the Welcome Keynote by George Grey, Linaro CEO discussing the various achievements since the last Linaro Connect in Budapest, and providing an insight to the future work to be done by the organization. The video is available on YouTube (embedded below), and since I watched it, I’ll provide a summary of what was discussed: Welcoming New Members – Kylin (China developed FreeBSD operating systems) joined LEG (Enterprise Group), NXP added LHG (Home Group) membership, and Xilinx joined LITE (IoT and Embedded). Achievements OPTEE open portable trusted environment execution more commonly integrated into products. Details at optee.org. LEG 17.08 ERP release based on Linux 4.12, Debian 8.9 with UEFI, ACPI, DPDK, Bigtop, Hadoop, etc… LITE group has been involved in Zephyr 1.9 release, notably contributing to LwM2M stack More projects to be found on download page. Open source future with many fields involved […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 4 Comments on Amazon EC2 F1 Instances Put Xilinx Virtex Ultrascale+ FPGA Boards into the Cloud

Amazon EC2 F1 Instances Put Xilinx Virtex Ultrascale+ FPGA Boards into the Cloud

We’ve covered several board and modules based on Xilinx Zynq Ultrascale+ MPSoC such as the AXIOM Board and Trenz TE0808 SoM, both featuring ZU9EG MPSoC, with systems selling for several thousands dollars. But I’ve been informed you may not need to purchase a board to use Virtex UltraScale+ FPGAs, which are different from Zynq UltraScale+ since they lack the ARM CPU & GPU and normally feature a more capable FPGA, as last November, Amazon launched a developer preview of F1 instances giving access to this type of hardware from their cloud. That’s the FPGA hardware you’ll be able to access from one F1 instance: Xilinx UltraScale+ VU9P manufactured using a 16 nm process. 64 GB of ECC-protected memory on a 288-bit wide bus (four DDR4 channels). Dedicated PCIe x16 interface to the CPU. Approximately 2.5 million logic elements. Approximately 6,800 Digital Signal Processing (DSP) engines. Virtual JTAG interface for debugging. I understand those FPGA boards are PCIe card plugged into […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 9 Comments on EU funded AXIOM Board is Powered by Xilinx Zynq UltraScale+ FPGA + ARM SoC

EU funded AXIOM Board is Powered by Xilinx Zynq UltraScale+ FPGA + ARM SoC

Back in 2015, Xilinx unveiled Zynq Ultrascale+ MPSoC combining ARM Cortex A53 & Cortex R5 cores, a Mali-400MP2 GPU, and UltraScale FPGA, and the company recently launched ZCU102 Evaluation Kit based on the SoC, which sells for just under $3,000. But if you are based in the European Union, you’ll be glad to learn about 4 millions Euros of your taxes have been spent to design a board based on the same MPSoC family as part of the AXIOM project, which was developed in collaboration with European universities and companies with the “aim of researching new software/hardware architectures for Cyber-Physical Systems (CPS) to meet the expectations” in terms of computational power, energy efficiency, scalability through modularity, easy programmability, and leverage of the best existing standards at minimal costs. AXIOM (Agile, eXtensible, fast I/O Module) board’s key specifications: SoC – Xilinx Zynq Ultrascale+ ZU9EG MPSoC with four ARM Cortex A53 cores @ 1.2GHz, two Cortex R5 “real-time” cores @ 500MHz, a […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 2 Comments on NovaVGA Shield Adds VGA Output to Arduino Boards

NovaVGA Shield Adds VGA Output to Arduino Boards

Arduino boards are convenient to control I/Os, link LEDs, and display info on small LCD displays, but if you want to output data to a larger monitor, it’s a bit more complex. NovaVGA shield for Arduino simplify the task of outputting data to a VGA monitor over SPI. NovaVGA shield hardware specifications: CPLD – Xilinx XC9572XL CPLD, user programmable via JTAG interface. SRAM Framebuffer – 160×120 pixels @ 6-bit color (2^6 = 64 possible colors) VGA Output – 640×480 @ 60Hz physical resolution (25.175MHz pixel clock) Interface with MCU – SPI mode 1 interface (consumes only three Arduino pins) Header pins not included MicroNova provides an Arduino library with various examples such as color palette, Mandelbrot, Tetris and text console, as well as a user’s guide and PDF schematics that can all be downloaded directly on the product page. NovaVGA shield sells for $29 on Tindie or directly on MicroNova store. Note that it’s not the first board of this […]

Posted on by Jean-Luc Aufranc (CNXSoft) - 5 Comments on SiFive Introduces Freedom U500 and E500 Open Source RISC-V SoCs

SiFive Introduces Freedom U500 and E500 Open Source RISC-V SoCs

Open source used to be a software thing, with the hardware design being kept secret for fear of being copied, but companies such as Texas Instruments realized that from a silicon vendor perspective it would make perfect sense to release open source hardware designs with full schematics, Gerber files and SoM, to allow smaller companies and hobbyists, as well as the education market, normally not having the options to go through standard sales channels and the FAE (Field Application Engineer) support, to experiment with the platform and potentially come up with commercial products. That’s exactly what they did with the Beagleboard community, but there’s still an element that’s closed source, albeit documented: the processor itself. But this could change soon, as SiFive, a startup founded by the creators of the free and open RISC-V architecture, has announced two open source SoCs with Freedom U500 processor and Freedom E300 micro-controller. Freedom U500 (Unleashed family) platform key specifications: U5 Coreplex with 1 […]