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ARMADA 8040 Networking Community Board with a Quad Core ARM Cortex A72 SoC Coming Soon for $300 and Up

Orange Pi Development Boards

Developers interested in ARMv8 server or networking boards are starting to have more and more affordable choices. After AMD Opteron A1100 series based LeMaker Cello board, and Softiron Overdrive 1000 server, SolidRun is now working on ARMADA 8040 networking community board powered by Marvell ARMA8040 quad core Cortex A72 network processor.

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ARMADA 8040 networking board (mrvl8040) preliminary specifications:

  • SoC – ARMADA 8040 (88F8040) quad core Cortex A72 processor @ up to 2.0 GHz with MoChi architecture
  • System Memory – 4GB DDR4 DIMM by default
  • Storage – 4x SATA 3.0 port + micro SD slot
  • Connectivity – 1x Gigabit RJ45 port, 1x SFP SGMII @ 2.5Gbps, dual 10Gbps copper with auto switchover to dual SFP+
  • Expansion – 1x PCIe-x4 3.0 slot, Linaro 96Boards expansion slot exposing GPIO, UART, I2C and SPI, Marvell TDM module header
  • USB – 1x USB 3.0 port, 2x micro USB ports
  • Debugging – Console port (UART) over microUSB connector; 20-pin Connector for CPU JTAG debugger; OpenOCD debugger support over FTDI device
  • Power Supply – 12V DC via power jack or ATX power supply
  • Dimensions – Mini-ITX form factor (170 mm x 170 mm)

The complete hardware specifications have not been released yet, so many of the features above are derived from the 3D renders of the board. The board targets OpenDataPlane (ODP), OpenFastPath (OFP) and ARM network functions virtualization (NFV) ecosystem communities. The software will include a fully open source ODP implementation with  U-Boot 2015.x, mainline U-Boot, UEFI EDK2, Linux LTS kernel 4.4.x, mainline Linux, Yocto 2.1 and netmap.

Marvell_ARMADA_8040_Block_Diagram

Marvell ARMADA 8040 Block Diagram

ARMADA 8040 community networking board is scheduled to ship early September (early access) or mid October, but SolidRun is already taking pre-orders with a $50 discount bringing the price down to $299 with 4GB RAM, but you may want to add the power supply for $10 more. Marvell also plans to launch 8-,16- and 32-core versions of ARMADA 8040 SoC in in Q1 2017, but it’s unknown whether they’ll make it in to community boards.

Via ElectronicsWeekly

  1. blu
    June 29th, 2016 at 15:02 | #1

    In SolidRun we trust. Don’t screw up this board, guys.

  2. TLS
    June 29th, 2016 at 20:16 | #2

    The black “square” looks like a x4 PCIe slot.

    It also looks like they’ve used up all the SERDES lanes in this design, which is quite impressive, as most companies don’t tend to do that when they design solutions using chips where you have to pick and chose what you implement.

    It’d be interesting to know what the cost for this SoC is, but I guess we’ll never know…

  3. kcg
    June 30th, 2016 at 02:26 | #3

    Nice price and configuration, let’s see if this happen at the end… Also it would be good if Marvel put some software reference guides on-line for this SoC as not everybody is using Linux…

  4. TLS
    June 30th, 2016 at 10:49 | #4

    @kcg
    Marvell is a funny company, you can’t really go to them as a customer and say, hey, I’d like to buy product xyz from you, as if they don’t think you’re a big enough customer, they won’t work with you.
    They also only provide software and development tools to companies they want to work with, unlike for example TI or NXP. That said, Marvell is not alone in this situation, in fact, at a previous job, we contacted a supplier who simply told us that “sorry, we’re not going to work with you, as we chose our customers”. It’s the kind of thing that really makes you wonder…

  5. June 30th, 2016 at 11:02 | #5

    @TLS
    I’ve had the same issue when I worked for smaller companies. Once I worked for a company whose website mentions that they specialize in “low volume manufacturing”, and many Silicon vendors refused to work with us, even when we said we don’t need support, we just want to be able to buy ICs (and get the SDK if relevant).

    I guess they want to focus the resources on larger customers. It’ also possible sales don’t get commissions at all if they don’t reach a minimum order level for a given customer.

  6. June 30th, 2016 at 14:01 | #6

    @kcg
    There will be open source firmwares, the device tree and all related to board and chip will be open.
    In some point Marvell will have the function specifications open too (reference manuals for the registers).

  7. June 30th, 2016 at 14:21 | #7

    A fix for the above –
    Connectivity – 1x RJ45 management port, 3x SFP cages (possibly one @ 10 Gb/s, two @ 2.5 Gb/s), 2x Gigabit Ethernet RJ45 ports

    It’s actually –
    – 1xRJ45 management port
    – 1xSFP SGMII @ 2.5Gbps
    – Dual 10Gbps copper with auto switchover to dual SFP+

    https://www.solid-run.com/marvell-armada-family/armada-8040-community-board/

  8. June 30th, 2016 at 14:29 | #8

    @rabeeh
    Thanks. The specs were not released at the time of writing, so I had to guess.

    I can see a 96Boards header, so does that mean the board will be an officially supported 96Boards?

  9. tkaiser
    June 30th, 2016 at 14:36 | #9

    @rabeeh
    Does the ‘switchover’ between copper and SFP+ happen individually eg. can I attach one 10Gbps copper port and one SFP+ and route/bridge between them? Any performance numbers available or is it too early to ask for that?

  10. June 30th, 2016 at 14:37 | #10

    cnxsoft :
    @rabeeh
    Thanks. The specs were not released at the time of writing, so I had to guess.
    I can see a 96Boards header, so does that mean the board will be an officially supported 96Boards?

    Marvell are working with Linaro on this; i’v forwarded them the question; lets see what happens.

  11. June 30th, 2016 at 14:41 | #11

    tkaiser :
    @rabeeh
    Does the ‘switchover’ between copper and SFP+ happen individually eg. can I attach one 10Gbps copper port and one SFP+ and route/bridge between them? Any performance numbers available or is it too early to ask for that?

    The switchover is on the phyiscal layer; i.e. the phy on the board decides to use the SFP+ or the 10G copper as interface out to the world.
    But it will only use either this or that.

    With regards the performance, it really depends on what workload (i.e. packet per second nat/routing/bridging/firewall, or TCP/IP termination like iperf).
    We just started working on the development board that we got from Marvell and it’s really an amazing device.

  12. tkaiser
    June 30th, 2016 at 15:12 | #12

    @rabeeh
    I have no doubt that this will be an amazing device! The Clearfog with its dual-core A9 (Armada 38x) is already amazing and outperforms every other SoC I tested so far when it’s about IO and network bandwidth (especially when combined) so being able to deal here with A72 and even more cores (virtualization!) and the offload engines and ODP support… really looking forward too.

    Thanks for the PHY clarification. I had some hope that with some SERDES voodoo it would be possible to bridge between 10GBASE-T and SFP+ at link speed and use the other RJ45 jack with 1GbE (had to buy a 10Gbps media converter recently for a customer… and for the price of this dumb converter I get your board + 4 8TB Seagate Archive HDD to be used as media converter + 30 TB Archive NAS). Didn’t look into ODP though so maybe the same is possible as with stock Linux kernel (bridging between 2 NICs and using the bridge device to be accessed by other hosts on the network).

  13. kcg
    June 30th, 2016 at 17:21 | #13

    @TLS
    Yes, I know Marvell well, that’s why I added this note. Honestly I’m yet to find company which would match quality and freeness of Freescale documentation. I hope NXP will not stop that. The question is when Freescale/NXP goes with their LS20x4 SoCs out ans especially their reference design boards — interested in this only from software developer perspective…

  14. kcg
    June 30th, 2016 at 17:22 | #14

    @rabeeh
    Source code of Linux drivers will not help that much (for BSDs), specs is way much better to write 3th party drivers. If this happen, then this will mean a change in Marvell practice I’ve seen so far… Would be good!

  15. kcg
    June 30th, 2016 at 17:31 | #15

    I need to add something: I’m kind of complaining about Marvell not publishing their SoCs specs for software development and I need to add to that Marvell behaves like any other company in the ARMv8 industry. In fact I’ve been able to find out software reference guides to only already mentioned Freescale/NXP SoCs and to Nvidia’s Tegra SoC. All other makers of very interesting SoCs simply do not publish, I mean: AMD (Opteron A1100), APM (X-Gene), Cavium (ThunderX).
    So big praise for Freescale/NXP and NVidia for doing that!

  16. June 30th, 2016 at 17:36 | #16

    kcg :
    I need to add something: I’m kind of complaining about Marvell not publishing their SoCs specs for software development and I need to add to that Marvell behaves like any other company in the ARMv8 industry. In fact I’ve been able to find out software reference guides to only already mentioned Freescale/NXP SoCs and to Nvidia’s Tegra SoC. All other makers of very interesting SoCs simply do not publish, I mean: AMD (Opteron A1100), APM (X-Gene), Cavium (ThunderX).
    So big praise for Freescale/NXP and NVidia for doing that!

    I understand that and fully agree with you. Even for Linux if you want to fix a bug you need device documentation.

    Just notice that Marvell has done that with the device that we have released with Clearfog (Armada 38x functional spec).
    You don’t need to sign NDA but a terms of use agreement –
    https://marvellcorp.wufoo.com/forms/marvell-armada-38x-functional-specifications/

    I know that this is not the ideal; but this is the compromise that was done.

  17. blu
    July 1st, 2016 at 13:38 | #17

    It’d be curious to know why Marvell went with the 2×2 clustering of cores, vs 4×1. I presume it had to do the design timeframe – with the lowest 8K series being a dual-core design, and building on that. But still a word from Marvell would be interesting.

  18. tkaiser
    July 1st, 2016 at 15:04 | #18

    @blu
    I doubt we’re talking about ‘2×2 clustering of cores’ and this is just a search&replace error in the product brief (according to PDF metadata the document for 8020 is the ‘master’ and the 8040 variant received last minute changes: photoshopped block diagram for example)

  19. blu
    July 1st, 2016 at 15:28 | #19

    @tkaiser
    Hmm. But the pdf wording is fairly non-ambiguous (http://www.marvell.com/embedded-processors/assets/Armada8040PB-Jan2016.pdf):

    ‘512 KB 16-way, set associative L2 cache per dual-core cluster’.

    According to that we can conclude their 8020 and 8040 designs are based off dual-core clusters. Basically the higher part is a ‘doubled’ version of the lower part, CPU-wise.

  20. tkaiser
    July 1st, 2016 at 15:56 | #20

    @blu
    The most important part when looking at the product brief PDFs is ‘Creator: Microsoft[TM] Office Word 2007’ so this sort of ‘technical documentation’ relies on copy&paste and search&replace (prone to manual errors). Check the 7040 product brief where it’s written correctly.

  21. Kelly
    September 17th, 2016 at 10:32 | #21

    Any guesses what size DIMM this will support? 4GB is great and all, but how much more could we put in?

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