ESP Open Source Research Platform Enables the Design of RISC-V & Sparc SoC’s with Accelerators

FOSDEM 2020 will take place next week, and there will be several interesting talks about open-source hardware and software development. One of those is entitled “Open ESP – The Heterogeneous Open-Source Platform for Developing RISC-V Systems” with an excerpt of the abstract reading:

ESP is an open-source research platform for RISC-V systems-on-chip that integrates many hardware accelerators.

ESP provides a vertically integrated design flow from software development and hardware integration to full-system prototyping on FPGA. For application developers, it offers domain-specific automated solutions to synthesize new accelerators for their software and map it onto the heterogeneous SoC architecture. For hardware engineers, it offers automated solutions to integrate their accelerator designs into the complete SoC.

ESP RISC-V & Sparc Platform
Click to Enlarge

If we go to the official website, we can see ESP (Embedded Scalable Platform) actually supports both 32-bit Leon3 (Sparc) and 64-bit Ariane (RISC-V) cores, and various hardware accelerators from the platform or third parties.


  • Architecture
    • Tile-based architecture: processor, memory and accelerator tiles
    • NoC (Network-on-Chip) based
    • Supports 32-bit Leon3 (Sparc) or 64-bit Ariane (RISC-V) cores
  • Accelerators
  • Design Flows
    • Seamless accelerator design flows:
      • RTL and Chisel
      • HLS from C and SystemC
      • Machine learning frameworks such as Keras/TensorFlow or PyTorch with hls4ml
    • Mix & match floorplanning GUI
    • Rapid FPGA prototyping

ESP is compatible with FPGA development boards such as Xilinx Virtex UltraScale+ FPGA VCU118, Xilinx Virtex-7 FPGA VC707, or proFPGA quad Virtex7 prototyping system, which in turn can run Linux SMP on the RISC-V or Sparc cores.

ESP was initially designed to run on CentOS 7 and is still the recommended OS, but Ubuntu 18.04 support has recently been added. Required components include various packages from the OS (Python, Perl, Qt, etc..), commercial tools from Cadence, Xilinx, and/or Mentors Graphics, as well as RISC-V and/or Sparc toolchains.

You can follow the tutorials for installing ESP on Centos or Ubuntu, and create your first single-core or multi-core SoC with ESP SoC Generator user interface as explained in the documentation.

ESP SoC Generator
Click to Enlarge

More tutorials are planned especially focused on the design of accelerators. If you’d like a more in-depth overview of the Embedded Scalable Platform, you may want to watch that 16-minute video published a few weeks ago.

Share this:

Support CNX Software! Donate via cryptocurrencies, become a Patron on Patreon, or purchase goods on Amazon or Aliexpress

ROCK 5 ITX RK3588 mini-ITX motherboard
Notify of
The comment form collects your name, email and content to allow us keep track of the comments placed on the website. Please read and accept our website Terms and Privacy Policy to post a comment.
4 years ago

Nice tool. The only downside is: it depends on Cadence and Mentor Graphics. It may be worth thinking about open source tools … example: (RTL to GDS, currently apha)

4 years ago

Nice TCL/TK GUI! Brings me memories from back in the days where I was doing perl+tcltk 🙂

Jeremy Herbert
Jeremy Herbert
4 years ago

> Open source research platform
> Required components include … commercial tools from Cadence, Xilinx and Mentor Graphics

So the open source platform (at the “Free and Open Source” conference no less) requires commercial closed source tools? huh?

4 years ago

The platform is open source. The embedded tools are not. There are relative easy ways to change this. I mentioned one open source toolchain. You may get the required open source tools from there. This way the open source platform becomes an open source developmet system.

Khadas VIM4 SBC