RISC-V International to give away 1,000 RISC-V development boards

The best way for a new platform to get good software support is to bring hardware into the hands of developers. That’s exactly what RISC-V International is doing by inviting developers to sign up for a RISC-V developer board sponsored by RISC-V and contributing members.

There are 1,000 boards on offer with 1GB to 16GB RAM depending on the target project from five companies and organizations namely Allwinner, Beagleboard.org, SiFive, Microchip Technology (previously Microsemi), and RIOS.

RISC-V development board giveaway

Here are the stated goals of the giveaway:

  • Spur innovation
  • Enable new opportunities for the next generation of developers to work with the RISC-V ISA
  • Provide a platform
    • For testing
    • To write programs that run on RISC-V
    • Develop software
    • Integrate existing software stacks
    • Optimize ecosystem software
  • Share feedback on the product such as ease to integrate software stacks, develop and test extensions, etc.

The company did not provide an exact list of development board but it should include Allwinner D1 SBC (1GB RAM), the upcoming low-cost PicoRio board, BeagleV development board with 4 to 8GB RAM, PolarFire SoC Icicle RISC-V board with penta–core RISC-V CPU and FPGA fabric (2GB RAM), as well as SiFive Unmatched mini-ITX motherboard with 16GB memory. All those boards are suitable for Linux and BSD development, it’s possible other boards will be offered as the goal is to distribute the free RISC-V development boards by June 2022.

If you want to apply, you can fill out your contact details and project information on a Google form. Membership status is asked, but the initiative is also open to non-members, although it’s not impossible members will get priority, as well as those part of an academic project.

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11 Replies to “RISC-V International to give away 1,000 RISC-V development boards”

  1. “the goal is to distribute the free RISC-V development boards by June 2022.” … so one year from now?
    Why not earlier? By June 2022, RISC-V has already achieved World Domination …

    1. Some boards will probably be sent very soon, but for example anybody working on the graphics stack may have to wait for boards with GPU. Those are not available yet. Notably, the PicoRio board may take a while. It will also take years before RISC-V gets an ecosystem that matches Arm.

      1. Isn’t the “graphics stack” just integrating a PowerVR IP block as similarly found in Beagle’s Sitara?

        The devil is in the detail, of course. Theoretically it’s just recompiling for risc-v the kernel shim code around a binary blob.

        1. Yes, but first we need to wait for the chips to be ready, because all RISC-V chips now come without GPU, so we’d need to wait for the hardware first.

          Then I can’t count the times I experienced “theory meets reality”, and that 5- minute task ends up being four-give hours of pure pain. Except here, we are probably talking months.

        2. Heh… It’s not QUITE as simple as that. Ever implement your own SOC in an ASIC or FPGA? I have. Dropping in a core like that takes a bit of lead time to get it to all work/play nice within the fabric there. Even if you’re raw masking it all out, you’re talking at least 6 months of initial prototype/verification and then to scale up takes at least another 3-6.

          1. From the software side you should have a defined interface and a programming model. You shouldn’t care about the internal fabric in the chip. From what I remember the device tree for the omap chips has a comment like “the internal bus is really a lot more complicated than this” and has a simplified model of it because it doesn’t matter to software.

            The problem with GPUs in the ARM world is you have some randomly configured IP block connected to a bus. Even something as basic as a UART will have the registers screwed with just for the fun of it so the hopes of a configurable GPU block just working with a generic driver is very low.

          2. you mean like 32-bit registers being split into two 16-bit regs 4 bytes apart probably 🙂

          3. These things happen when you design your SoC as a fancy 8051 with 32bit co-processors. 😉

      2. Precisely, Jen-Luc. It still amazes me how people think this stuff simply works in the same manners you would a PC… X-D

  2. Already got my request in. We’ll see. Hoping for a BeagleV or a Icicle board. (Let’s just say that buying the Icicle for me might be the biggest bang for buck on their part because I won’t have to spend $500 or so on that and can buy the other boards and go to town on Embedded Linux support, etc.

    The stack and ecosystem happens because you make the sharp tools and OS stuff that other people leverage…myself included. Since nobody was making the sharp tools I needed, I just took to making those as well… X-D

    1. >go to town on Embedded Linux support, etc.

      You’re going to blow everyone’s minds with a yocto meta layer?

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