Andes unveils AndesCore AX65 Out-of-Order RISC-V core for compute intensive applications

Andes Technology has unveiled the high-end AndesCore AX60 series out-of-order 64-bit RISC-V processors at the Linley Fall Processor Conference 2022 with the new cores designed for compute-intensive applications such as advanced driver-assistance systems (ADAS), artificial intelligence, augmented/virtual reality, datacenter accelerators, 5G infrastructure, high-speed networking, and enterprise storage.

AndesCore AX65 is the first member of the family and supports RISC-V scalar cryptography extension and bit manipulation extension. It is a 4-way superscalar core with Out-of-Order (OoO) execution in a 13-stage pipeline and can fetch 4 to 8 instructions per cycle.

AndesCore AX60

The company further explains the AX65 core then decodes, renames, and dispatches up to 4 instructions into 8 execution units, including 4 integer units, 2 full load/store units, and 2 floating-point units. The AX65’s memory subsystem also includes split 2-level TLBs (translation lookaside buffers) with up to 64 outstanding load/store instructions.

Up to eight AX65 cores (or should that then be AX65MP cores?) can be packed into a cluster with up to 8MB shared cache and with each core having 64KB instruction and data caches. Andes also added a RISC-V standard external debug and instruction trace interfaces for development and debugging.

Performance-wise, the new AX65 offers twice the performance “in large benchmarks” over the AndesCore AX45 at the same frequency, but in most cases, it should run even faster since the core can reach up to 2.5GHz when manufactured with a 7nm process, or about 25% higher than what the AX45 is capable of.

Again it will take a while before AndesCore AX65 SoCs become commercially available because we’re told the new high-end RISC-V core will be available to “lead customers” in mid-2023, while general customers will get access to it at the end of 2023. That should probably mean the first commercial products based on AX65 will be launched sometime in 2024 or 2025. A few more details can be found in the press release as there’s no product page just yet.

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2 Replies to “Andes unveils AndesCore AX65 Out-of-Order RISC-V core for compute intensive applications”

  1. I wonder how it fares against the new SiFive P670
    Both seems to do 4 instruction OOO, with up to 4 integer units, 2 load/store and 2 floating point operations every cycle.
    The P670 also has a vector unit, but lets ignore that for the comparison (scalar code only).

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