NXP i.MX 95 processor features Cortex-A55, Cortex-M33, and Cortex-M7 cores, eIQ Neutron NPU

NXP i.MX 95 is an upcoming Arm processor family for automotive, industrial, and IoT applications with up to six Cortex-A55 application cores, a Cortex-M33 safety core, a Cortex-M7 real-time core, and NXP eIQ Neutron Neural Network Accelerator (NPU).

We’re just only starting to see NXP i.MX 93 modules from companies like iWave Systems and Forlinx, but NXP is already working on its second i.MX 9 processor family with the i.MX 95 application processor family equipped with a higher number of Cortex-A55 cores, an Arm Mali 3D GPU, NXP SafeAssure functional safety, 10GbE, support for TSN, and the company’s eIQ Neutron Neural Processing Unit (NPU) to enable machine learning applications.


NXP i.MX 95 specifications:

  • CPU
    • Up to 6x Arm Cortex-A55 cores with 32KB I-cache, 32KB D-cache, 64KB L2 cache, 512KB L3 cache with ECC
    • 1x Arm Corex-M7 real-time core with 32KB I-cache, 32KB D-cache, 512KB TCM with ECC
    • 1x Arm Cortex-M33 low-power safety microcontroller with 16KB I-cache, 16KB D-cache, 256KB OCRAM with ECC
  • GPU – Unnamed Arm Mali 3D GPU with OpenGL ES 3.2, Vulkan 1.2, OpenCL 3.0, 2D GPU
  • AI accelerator – NXP eIQ Neutron NPU
  • Memory I/F – Up to 6.4GT/s x32 LPDDR5/LPDDR4x (w/ Inline ECC)
  • Storage I/F
    • 3x SD 3.0/SDIO3.0/eMMC 5.1
    • 1x Octal SPI, including support for SPI NOR and SPI NAND memories
  • Display I/F
    • 1x 4-lane MIPI-DSI (2.5 Gbps/lane) supporting up to 4kp30 or 3840x1440p60
    • 2x 4-lane or 1x 8-lane LVDS up to 1080p60
  • Camera I/F
    • 2x 4-lane MIPI-CSI and ISP (2.5 Gbps/lane) with PHY (1 mux with DSI); up to 500 Mpixel/s
    • Up to 2x 4Kp30, 4x 1080p60, or 8x 1080p30 cameras with MIPI virtual channels
  • Audio
    • 17x I2S TDM (32-bit @ 768KHz), SPDIF Tx/Rx, eArc Rx
    • 8-channel PDM microphone input
    • MQS: Medium Quality Sound output (sigma-delta modulator)
  • Networking – 1x 10GbE, 2x Gigabit Ethernet with TSN; AVB & IEEE 1588 for sync, and EEE for low power.
  • USB – 1x USB 3.0 Type-C with PHY + 1x USB 2.0 Type-C with PHY
  • PCIe – 2x PCIe Gen 3 1x lane
  • Serial
    • 5x CAN-FD
    • 8x UART/USART/Profibus
  • Other peripherals
    • 8x I2C, 8x SPI, 2x I3C
    • 1x 8-ch, 12-bit ADC
    • 2x 32-pin FlexIO interfaces (camera, bus, or serial I/O)
  • Security & Safety
    • NXP EdgeLock secure enclave
    • NXP SafeAssure functional safety to enable ISO 26262 ASIL-B and SIL-2 IEC 61508 compliant platforms
  • Packaging
    • 19×19 mm2 0.7 mm pitch
    • 15×15 mm2 0.5 mm pitch
  • Temperature Ranges
    • Consumer – 0 ºC to 95 ºC
    • Standard Industrial – -40 ºC to 105 ºC
    • Automotive / Extended industrial – -40 ºC to 125 ºC
  • Process – 16nm FinFET

Compared to the i.MX 93, the i.MX 95 has much better multimedia capabilities with a 3D GPU, and support for higher-resolution displays and cameras. There’s also a 4K VPU that could be a hardware video decoder/encoder (Video Processing Unit), but NXP did provide details so it remains to be confirmed, since VPU could also be something else. The i.MX 95 also integrates a range of high-speed interfaces with 10GbE, USB 3.0, and PCIe that will allow, for instance, the addition of wireless connectivity such as WiFi, satellite radio, or 5G.

NXP will provide Linux and Android BSP for the Cortex-A55 cores, while the Cortex-M33 and Cortex-M7 real-time cores will run FreeRTOS. The eIQ Neutron NPU, for which we have limited information, will be supported by the eIQ machine learning software development environment. The NXP i.MX 95 will power “advanced applications” in automotive, industrial, IoT, networking, human-machine interface (HMI), etc…

NXP i.MX 95 processors are expected to start sampling in H2 2023 to lead customers, meaning we’ll probably see the first NXP i.MX 95 system-on-modules and single board computers at the beginning of 2024. More details may be found on the product page and CES 2023 press release.

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2 Replies to “NXP i.MX 95 processor features Cortex-A55, Cortex-M33, and Cortex-M7 cores, eIQ Neutron NPU”

  1. Went to a NXP talk, chip is quite impressive for the right application (it’s not a set top box MPU). Note that lack of HDMI, DP, or similar display output. Expected availability is something like Q1 2025, price hasn’t been set yet, but will be more than i.MX8 series. NXP emphasized their commitment to providing long term, up to date, and comprehensive support for Linux (for A55) and RTOS (for M7, M33).

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