RISC-V based PolarFire SoC FPGA by Microsemi may be coming up in the third quarter of this year, but Ali Uzel has been sharing a few details about SAVVY-V advanced open-source RISC-V cluster board made by FOSOH-V (Flexible Open SOurce Hardware for RISC-V) community of developers.
It’s powered by Microsemi Polarfire RISC-V SoC MPFS250T with four 64-bit RISC-V cores, a smaller RV64IMAC monitor core, and FPGA fabric that allows 10GbE via SFP+ cages, and exposes six USB Type-C ports. The solution is called a cluster board since up to six SAVVY-V boards can be stacked via a PC/104+ connector and interfaced via the USB-C ports.
SAVVY-V cluster board preliminary features and specifications:
- SoC – Microsemi Polarfire RISC-V SoC MPFS250T with a quad-core 64-bit RV64IMAFDC (RV64GC) processor @ up to 667 MHz, a RV64IMAC monitor core, and FPGA fabric with 250K logic elements; 3.0 CoreMarks/MHz, 2.0 DMIPs/MHz; Also compatible with MPFS160T, MPFS095T, andMPFS025T.
- System Memory
- Up to 4GB 32-bit 3200Mbps LPDDR4 for MSS (4+1 core Microprocessor Sub-System)
- Up to 2GB 16-bit 1333Mbps LPDDR3 for programmable switch fabric (FPGA)
- Storage
- Up to 1Gbit NOR Flash.
- Up to 1TB storage via 4x eMMC 5.1 chip on the same EMMC bus of SoC thru mux/demux. Each eMMC 5.1 chip can have a maximum of 256GB of capacity.
- I2C EEPROM for board parameters
- MicroSD slot via SPI
- Networking
- 2x SFP+ connectors for 1/10Gbps Ethernet. Power switch used to manage SFP powering.
- 2x RJ45 connectors for Gigabit Ethernet.
- USB – 1x USB 2.0 micro AB receptacle connector as host up to 5V @ 900 mA (adjustable up to 1.5A)
- Security
- Embedded Athena TeraFire F5200B side-channel resistant crypto coprocessor for “S” version of Polarfire SoC.
- Defense-grade Security, RISC-V Physical Memory Protection (PMP).
- Expansion
- Right-angle header for add-on 19x LED board with Power-on, Reset, Alarm, Ethernet, Root/EP, PCIe Link, and general-purpose LEDs.
- Cluster Interfaces
- Stackable thru PC/104+ connector with Power & GND, SPI, I2C, 6 x GPIO, Common Cluster Reset(CCR), 1x programmable LVDS clock, Polarfire SoC Probe_P&N
- PCIe Gen 2 (5GT/s) bandwidth via USB Type-C connectors between any board in a cluster (up to 6 x SAVVY-V boards)
- One board working as PCIe root can serve up to five boards in EP mode.
- Debugging
- 1x micro USB 2.0 port for USB –UART debug.
- ESD protected debug headers: JTAG, UART, I2C, MDC/MDIO, QSPI
- Misc – Two Reset push-buttons for single board and cluster, on-board supervisor monitors all logic voltages and generates reset, 2x headers for 5V fans, RTC + battery holder
- Power Supply – Single 12VDC/15VDC @ 7A max. nominal input thru a screw terminal connector per SAVVY-V board. Support for dual power supply for redundancy
- Power Consumption – Less than 20W for full configuration and fanless mode
- Dimensions – ~18 x 12 x 2 cm
The FPGA resources are said to allow developers to customize the cluster for various types of applications including RISC-V ISA extensions, artificial intelligence, blockchain, and more. AFAICT there’s not interface that could be used to add graphics support, so it’s strictly for headless applications. There’s no mention about the operating system for the board, but Microsemi claims deterministic, real-time Linux support for their PolarFire RISC-V SoC FPGA.
I was told the board would be produced, and possibly as soon as September/October. That’s about all information I have for now. You can find a few details and/or get updates about the project by following Ali Uzel on LinkedIn and/or joining FOSOH-V group, also on LinkedIn.
Jean-Luc started CNX Software in 2010 as a part-time endeavor, before quitting his job as a software engineering manager, and starting to write daily news, and reviews full time later in 2011.
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