Alif Ensemble Cortex-A32 & Cortex-M55 chips feature Ethos-U55 AI accelerator

Alif Semiconductor’s Ensemble is a family of processors and microcontrollers based on Arm Cortex-A32 and/or Cortex-M55 cores, one or two Ethos-U55 AI accelerators, and plenty of I/Os and peripherals.

Four versions are available as follows:

  • Alif E1 single-core MCU with one Cortex-M55 core @ 160 MHz, one Ethos U55 microNPU with 128 MAC/c
  • Alif E3 dual-core MCU with one Cortex-M55 core @ 400 MHz, one Cortex-M55 core @ 160 MHz, one Ethos U55 with 256 MAC/c, one Ethos U55 with 128MAC/c
  • Alif E5 triple-core fusion processor with one Cortex-A32 cores @ 800 MHz, one Cortex-M55 core @ 400 MHz, one Cortex-M55 core @ 160 MHz, one Ethos U55 with 256 MAC/c, one Ethos U55 with 128MAC/c
  • Alif E7 quad-core fusion processor with two Cortex-A32 cores @ 800 MHz, one Cortex-M55 core @ 400 MHz, one Cortex-M55 core @ 160 MHz, one Ethos U55 with 256 MAC/c, one Ethos U55 with 128MAC/c

As you can see from the table below, Alif Semiconductor also offers the Crescendo family (C1, C3, C5, C7) with the same configurations, but adding LTE Cat-M1/NB1/NB2 wireless, integrated SIM cellular subscriber management, and GNSS positioning.


Alif Ensemble Cortex-A32 Cortex-M55 processors

Let’s look at the Alif Semi E7 specifications in more detail:

  • Quad-Core Fusion processor
    • 1x dual Arm Cortex-A32 Cores with Arm Neon SIMD Extension up to 800 MHz, 512KB Shared L2, 32KB L1 Instruction and Data Caches, MMU, Armv8-A ISA with Arm TrustZone
    • 1x Arm Cortex-M55 Core up to 400 MHz, with Helium Vector Processing Extension, 1.25MB SRAM, 32KB Instruction and Data cache, Armv8.1-M ISA with Arm TrustZone
    • 1x Arm Cortex-M55 Core up to 160 MHz, with Helium Vector Processing Extension, 512KB of ECC Protected SRAM, 32KB Instruction and Data caches, Armv8.1-M ISA with Arm TrustZone
  • GPU – D/AVE 2D graphics processing unit
  • Micro NPUs – 2x Arm Ethos-U55 Neural Processing Units, one up to 204 GOPS, the other up to 46 GOPS
  • On-chip application memory
    • Up to 5.5 MRAM Non-Volatile Memory
    • Up to 13.5 MB SRAM
  • External memory interfaces
    • 2x Octal SPI
    • 1x SD v4.2, eMMC v5.1
  • Display interfaces
    • 2-lane MIPI DSI
    • 1x Display Parallel Interface (DPI) up to 24-bit RGB
  • Camera interfaces
    • 2-Lane MIPI CSI-2
    • Camera Parallel Interface (CPI), up to 16 bits
    • Low-power CPI, up to 8 bits
  • Audio Interfaces
    • 4x I2S, 1x low-power I2S
    • 4x 2-channel PDM microphone inputs
    • 4x 2-channel low-power PDM microphone inputs
  • General Input/Output
    • Up to 120x 1.8V GPIOs (shared with peripherals)
    • Up to 8x selectable 1.8V to 3.3V GPIOs (shared with peripherals)
  • Communication interfaces
    • 1x 10/100M Ethernet with DMA
    • 1x USB 2.0 HS/FS Host/Device with DMA
    • 1x SDIO v4.1 channel with DMA
    • 1x CAN FD
    • 1x MIPI I3C
    • 4x I2C up to 1 Mbps, 1x low-power I2C
    • 8x UART up to 2.5 Mbps (4x with RS-485 driver control), 1x low-power UART
    • 4x SPI up to 50 Mbps, 1x low-power SPI
  • Analog interfaces
    • 3x 12-bit ADCs, 1x 24-bit ADC
    • 2x 12-bit DACs
    • 4x high-speed analog comparators with 2.5 ns response (4× 4 Inputs)
    • 1x low-power analog comparator
    • Internal Temperature Sensor
    • Internal Precision Reference Voltage
  • Timing control and measurement
    • 12x universal 32-bit timers capable of motor and LED lighting control
    • 4x watchdog timers
    • 4x low-power 32-bit timers
    • 1x real-time Counter
    • 4x quadrature encoder counters
  • Clock Generation
    • Internal low-frequency and high-frequency RC oscillators
    • External low-frequency and high-frequency crystal oscillators
    • 1x user PLL
  • Secure Enclave
    • Hardware-based Root-of-Trust with Unique Device ID
    • Secure Key Generation and Storage, Secure Certificate Storage
    • Factory-provisioned Private Keys
    • Crypto Accelerators—AES (up to 512), ECC, SHA, RSA, and TRNG
    • Secure Debugging with Certificate Authentication
  • Misc
    • 3x 32-channel DMA Controllers
    • CRC accelerator with programmable polynomials
    • Programmable low supply voltage detection warning
    • Power-On Reset and Brown Out Reset
    • Real-Time Clock (RTC)
    • JTAG/SWD debug interface
  • Power management
    • Primary supply voltage – 1.71 V to 3.6 V
    • I/O supply voltage – 1.2 V to 1.8 V
    • Battery backup supply voltage – 1.62 V to 3.6 V
    • Autonomous Intelligent Power Management (aiPM)
    • Power Domains – Dynamic power, gating, voltage and clock scaling, DC-DC converter
    • Power consumption
      • 885 nA Consumed in STOP Mode with LPRTC; 4KB SRAM is Retained, Wake Pins, BOR
      • As Low as 18 µA/MHz dynamic consumption for Cortex-M55
  • Packages
    • WLCSP208, 0.5 mm Pitch
    • DRQFN164, 0.5 mm Pitch
  • Temperature range – -40°C to 85°C
  • Process – FD-SOI low leakage process
Alif E7 processor block diagram
Simplified block diagram for Alif E7 processor
Alif Ensemble development board
Alif Ensemble development board

The inclusion of the Ethos-U55 makes the Ensemble family much more powerful and power efficient for AI/ML workloads than microcontrollers based on a Cortex-M55 microcontroller only. Testing with MobileNet V2.1.0 model for object classification, Alif Semiconductor found out a Cortex-M55 + Ethos-U55 microcontroller (that must be the Alif E1) was 800 times faster than a previous generation Cortex-M microcontroller, 78 times faster (8ms vs 624ms inference) and 76x more efficient (3 vs 228 mJ) compared to a Cortex-M55 alone.

Alif Semiconductor E5 single and E7 dual-core Fusion processors can run Linux on the Cortex-A32 core, and target security, AI/ML, graphics, and imaging applications such as building automation, EV charging station, PoS, robotics, home appliances, and HMI control panel. The E1 and E3 single and dual-core microcontrollers should be in barcode scanners, failure prevention systems, portable healthcare devices, lighting control systems, smart home applications, and industrial control systems.

YouTube video player

There’s also a development board, but most documentation, including datasheets, guides, and software, requires an email registration with approval from the company, which was not given to me at the time of writing this article. But we can find a few more details in some videos posted on YouTube such as the Ensemble development kit unboxing video above, where we notably learn that the “kits are available now through your Arrow representative” followed by “Please note you need to work with a dedicated inside sales representative to purchase our kit, as these are not available online”.

More details can be found on the company’s website.

Thanks to Loïc for the tip.

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10 Replies to “Alif Ensemble Cortex-A32 & Cortex-M55 chips feature Ethos-U55 AI accelerator”

  1. This is the first time I’ve seen a Cortex-A32 actually getting put into a production chip. It’s been 6 years since the original announcement and I had expected everyone to just go with the slightly larger but otherwise identical Cortex-A35 that includes both 32-bit and 64-bit modes.

    I wonder what motivated Alif to make this point pick, did Arm changing their pricing to make Cortex-A32 more attractive compared to A7 and A35?

    1. Good point, however I suspect that it’s not so much a matter of pricing as power consumption. I’ve long thought that 64-bit register files are quite heavy when you’re trying to save the last drop of power.

      1. I checked Arm’s marketing pages, which list a 10% energy and size advantage over a Cortex-A35. In most systems this would not be worth it, given that an A35 CPU core is only a tiny bit of the total budget compared to 3D-GPU, NPU, LP-DDR4, PCI, etc.

        On this particular chip, it looks like it actually does matter, because all of the usual power hungry units are absent. And given that there is only 18MB of RAM (eMRAM plus SRAM), you wouldn’t be able to run a 64-bit Linux kernel anyway, so the decision seems entirely sensible.

        I wonder what kind of application they expect to run on Linux with these tight memory constraints, but this would be one of the most power efficient Linux systems ever if someone has the right use case.

  2. Once more Alif announces something that looks too good to be true, there has to be a con and I bet it’s availability, not just now, but for entire lifecycle, given current Arrow situation.

        1. So am I, it hurts to see, as I’d love to introduce E7 as an alternative to the current brains of a certain academic project, maybe even design E1 feather, for all those sensor-based ML with actuation projects it seems perfect, but with such access restrictions either application seems like a risk.

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