Earlier today, Intel announced the Elkhart Lake IoT edge processor family, and as well as more 15W Tiger Lake Core i3/i5/i7 UP3 processors designed for IoT & embedded applications, and with a configurable TDP from 12W to 28W.
ADLINK Technology is leveraging existing and those new Tiger Lake UP3 processors with the cExpress-TL COM Express Type 6 module based on the various Intel Core i7/i5/i3 and Celeron Tiger Lake UP3 SKUs delivering three times the AI inferencing performance of older platforms thanks to AVX-512 Vector Neural Network Instructions (AVX512 VNNI) instructions and equipped with the latest PCIe Gen4 expansion interface.
cExpress-TL COM Express Tiger Lake module specifications:
- SoC (one or the other)
- Intel Core i7-1185G7E quad-core/octa-thread processor with 12MB cache, Intel Iris Xe graphics with 96x EU; up to 28W TDP (cTDP 15W)
- Intel Core i5-1145G7E quad-core/octa-thread processor with 8MB cache, Intel Iris Xe graphics with 80x EU; up to 28W TDP (cTDP 15W)
- Intel Core i3-1115G4E dual-core/quad-thread processor with 6MB, Intel UHD graphics with 48EU; Up to 28W TDP (cTDP 15W)
- Intel Celeron processor with 4MB cache, 15W (Note: if that’s also a Tiger Lake processor then it has not been announced).
- System Memory- Up to 64GB via two DDR4 SO-DIMM sockets up to 3200 MT/s IBECC (in-band ECC)/non-ECC
- COM Express board-to-board connectors with
- Storage – 2x SATA 6Gb/s
- Video Interfaces – Combination of DisplayPort, HDMI, LVDS, eDP or VGA outputs for up to 4x 4Kp60 independant displays, and 2x 8Kp60 displays
- Audio – Support for ALC886 on carrier board
- Networking – 2.5GbE via Intel i225 series TSN MAC/PHY
- USB – 4x USB 3.2 and 4x USB 2.0
- Serial – 2x UART ports with console redirection
- 5x PCIe x1 Gen3 (AB): Lanes 0/1/2/3 (configurable to 4 x1, 2 x2, 1 x4, 2 x1 + 1 x2, 1 x2 + 2 x1) and Lane 4 (x1 only)
- 1x PCIe x4 Gen4 (CD): Lanes 16-19 (only x4) up to 16 GT/s
- Low Speed Interfaces – LPC bus, SMBus (system) , I2C (user)
- GPIO – 4x GPO and 4x GPI
- Misc – SEMA Board Controller with Voltage/current monitoring, power sequence debug support, AT/ATX mode control, watchdog timer, etc..
- BIOS – 16MB or 32MB flash for AMI UEFI Embedded BIOS (optional failsafe dual-BIOS support)
- Debug Header – 30-pin multipurpose flat cable connector for use with DB-30 x86 debug module
- HW – Security – InfineonTPM 2.0
- Power Supply
- Standard Input – ATX: 12V/ 5V or AT: 12V
- Wide Input – ATX: 8.5-20 V / 5V or AT: 8.5-20V
- ACPI 5.0 compliant, Smart Battery support
- DImensions – 95 x 95 mm (PICMG COM.0 Rev 3.0 Type 6)
- Temperature Range
- Standard: 0°C to 60°C (Storage: -20°C to 80°C)
- Extreme Rugged: -45°C to +85°C
- Humidity – 5-90% RH operating, non-condensing; 5-95% RH storage (and operating with conformal coating)
- Shock and Vibration
- IEC 60068-2-64 and IEC-60068-2-27
- MIL-STD-202F, Method 213B, Table 213-I, Condition A and Method 214A, Table 214-I, Condition D
Compared to their non-embedded versions, the new Tiger Lake UP3 processors are clocked at a slightly lower frequency in order to support a wider operating temperature range. This allows ADLINK cExpress-TL COM Express module to be found integrated into applications for transportation, healthcare, industrial automation and control, edge controllers, robotics, and multi-camera-based AI solutions.
Visit the product page or more information about the cExpress-TL COM Express module.
Jean-Luc started CNX Software in 2010 as a part-time endeavor, before quitting his job as a software engineering manager, and starting to write daily news, and reviews full time later in 2011.
7 Replies to “Intel Tiger Lake UP3 COM Express Module Offers High AI Performance, PCIe Gen4 Interface”
Does anyone here have an idea what in-band ECC means? Thanks!
I found it described here: https://www.freepatentsonline.com/20190332469.pdf After a quick glance, it seems to use addressable memory instead of extra chips to store ECC information. If that’s the case that would mean that you could possibly use regular DDR modules and have ECC by reducing the amount of memory a little bit (typically by 1/8) because the memory controller would store the information in other lines.
Very interesting reading! Thanks a lot for the link!
In-Band ECC provides ECC protection without additional ECC device & data pins where a portion of DRAM space is reserved to store ECC data and ECC data is transferred “In Band” on existing data pins. So it’s basically more cost effective solution compared to the traditional ECC.ADLINK seems to be an early adopter of IBECC on COM Express modules.
Seriously, I get a blocking full page ad when clicking on an article on the main page (on iPhone)? Some advertising is just too much.
I think those are called vignette ads. I’ve just disabled those in Google Auto Ads, so they should not appear anymore.
It looks like you disabled the right ones indeed. I only used to see them using a single browser (the slower, in addition) and indeed they were pretty annoying in that they wouldn’t even disappear without clicking on the top right corner. They would always appear when directly clicking on an article from the main page but not when opening it in a new tab. Now they don’t appear anymore, thanks for this!